Terasic TR-5 Lite FPGA, User Manual

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TR5-Lite User Manual 37 www.terasic.com
June 20, 2018
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The development board has two independent 10G SFP+ connectors that use one transceiver channel
each from the Stratix V GX FPGA device. These modules take in serial data from the Stratix V GX
FPGA device and transform them to optical signals. The board includes cage assemblies for the
SFP+ connectors. Figure 2-10 shows the connections between the SFP+ and Stratix V GX FPGA.
Figure 2-10 Connection between the SFP+ and Stratix V GX FPGA
Table 2-17 and Table 2-18 list ists the QSF+ A and B pin assignments and signal names relative to
the Stratix V GX device.
Table 2-17 SFP+ A Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description I/O Standard
Stratix V GX
Pin Number
SFPA_TX_p Transmiter data 1.4-V PCML PIN_AY6
SFPA_TX_n Transmiter data 1.4-V PCML PIN_AY5
SFPA_RX_p Receiver data 1.4-V PCML PIN_BB2
SFPA_RX_n Receiver data 1.4-V PCML PIN_BB1
SPFA_LOS Signal loss indicator 2.5V PIN_AW24
SPFA_MOD0_PRSNT_n Module present 2.5V PIN_BA25
SPFA_MOD1_SCL Serial 2-wire clock 2.5V PIN_BA24
SPFA_MOD2_SDA Serial 2-wire data 2.5V PIN_BB26
SPFA_RATSEL0 Rate select 0 2.5V PIN_AY25
SPFA_RATSEL1 Rate select 1 2.5V PIN_AV25