Terasic TR-5 Lite FPGA User Manual Download

Page: 34 / 86

TR5-Lite User Manual

www.terasic.com

June 20, 2018

QDRIIC_D16

Write data bus[16]

1.8-V HSTL Class I

PIN_G20

QDRIIC_D17

Write data bus[17]

1.8-V HSTL Class I

PIN_T21

QDRIIC_Q0

Read Data bus[0]

1.8-V HSTL Class I

PIN_U24

QDRIIC_Q1

Read Data bus[1]

1.8-V HSTL Class I

PIN_P24

QDRIIC_Q2

Read Data bus[2]

1.8-V HSTL Class I

PIN_M23

QDRIIC_Q3

Read Data bus[3]

1.8-V HSTL Class I

PIN_U23

QDRIIC_Q4

Read Data bus[4]

1.8-V HSTL Class I

PIN_T23

QDRIIC_Q5

Read Data bus[5]

1.8-V HSTL Class I

PIN_T24

QDRIIC_Q6

Read Data bus[6]

1.8-V HSTL Class I

PIN_P23

QDRIIC_Q7

Read Data bus[7]

1.8-V HSTL Class I

PIN_R24

QDRIIC_Q8

Read Data bus[8]

1.8-V HSTL Class I

PIN_N23

QDRIIC_Q9

Read Data bus[9]

1.8-V HSTL Class I

PIN_J24

QDRIIC_Q10

Read Data bus[10]

1.8-V HSTL Class I

PIN_H24

QDRIIC_Q11

Read Data bus[11]

1.8-V HSTL Class I

PIN_F24

QDRIIC_Q12

Read Data bus[12]

1.8-V HSTL Class I

PIN_J25

QDRIIC_Q13

Read Data bus[13]

1.8-V HSTL Class I

PIN_H23

QDRIIC_Q14

Read Data bus[14]

1.8-V HSTL Class I

PIN_L24

QDRIIC_Q15

Read Data bus[15]

1.8-V HSTL Class I

PIN_F25

QDRIIC_Q16

Read Data bus[16]

1.8-V HSTL Class I

PIN_K24

QDRIIC_Q17

Read Data bus[17]

1.8-V HSTL Class I

PIN_K25

QDRIIC_BWS_n0 Byte Write select[0]

1.8-V HSTL Class I

PIN_L21

QDRIIC_BWS_n1 Byte Write select[1]

1.8-V HSTL Class I

PIN_P21

QDRIIC_K_p

Clock P

Differential 1.8-V HSTL Class I

PIN_N22

QDRIIC_K_n

Clock N

Differential 1.8-V HSTL Class I

PIN_M22

QDRIIC_CQ_p

Echo clock P

1.8-V HSTL Class I

PIN_L23

QDRIIC_CQ_n

Echo clock N

1.8-V HSTL Class I

PIN_K26

QDRIIC_RPS_n

Report Select

1.8-V HSTL Class I

PIN_K21

QDRIIC_WPS_n

Write Port Select

1.8-V HSTL Class I

PIN_T22

QDRIIC_DOFF_n PLL Turn Off

1.8-V HSTL Class I

PIN_E26

QDRIIC_ODT

On-Die

Termination

Input

1.8-V HSTL Class I

PIN_G25

QDRIIC_QVLD

Valid Output Indicator 1.8-V HSTL Class I

PIN_H25

Table 2-16

QDRII+ SRAM D Pin Assignments, Schematic Signal Names, and Functions

Schematic

Signal Name

Description

I/O Standard

Stratix IV GX Pin

Number

QDRIID_A0

Address bus[0]

1.8-V HSTL Class I

PIN_U26

QDRIID_A1

Address bus[1]

1.8-V HSTL Class I

PIN_T27

Summary of Contents for TR-5 Lite FPGA

Page 1: ...TR5 Lite User Manual 1 www terasic com June 20 2018...

Page 2: ...NSOR AND FAN CONTROL 19 2 5 CLOCK CIRCUIT 20 2 6 RS 422 SERIAL PORT 21 2 7 FLASH MEMORY 22 2 8 DDR3 SDRAM 25 2 9 QDRII SRAM 29 2 10 SPF 37 2 11 PCI EXPRESS 38 2 12 SATA 40 CHAPTER 3 SYSTEM BUILDER 42...

Page 3: ...2 SI570 EXAMPLE BY RTL 59 5 3 SI570 AND CDCM PROGRAMMING BY NIOS II 67 CHAPTER 6 MEMORY REFERENCE DESIGN 72 6 1 QDRII SRAM TEST 72 6 2 DDR3 SDRAM TEST 75 6 3 DDR3 SDRAM TEST BY NIOS II 78 CHAPTER 7 TR...

Page 4: ...integrated transceivers that transfer at a maximum of 12 5 Gbps allowing the TR5 Lite to be fully compliant with version 3 0 of the PCI Express standard as well as allowing an ultra low latency straig...

Page 5: ...2 push buttons o 2 position DIP switch On Board Clock o 50MHz Oscillator o Programmable oscillators Si570 and CDCM61004 Memory o DDR3 SDRAM o QDRII SRAM o FLASH Communication Ports o Two SFP connector...

Page 6: ...a am m Figure 1 1 shows the block diagram of the TR5 Lite board To provide maximum flexibility for the users all key components are connected with the Stratix V GX FPGA device Thus users can configure...

Page 7: ...ocks 2 PCI Express hard IP blocks 840 user I Os 210 full duplex LVDS channels 28 phase locked loops PLLs JTAG Header and FPGA Configuration On board JTAG header for use with the Quartus II Programmer...

Page 8: ...o SFP ports Two SFP connector 10 Gbps PCI Express x8 edge connector Support PCIe Gen1 2 3 Connection established with PC motherboard with x8 or x16 PCI Express slot Power Source PCI Express 6 pin DC 1...

Page 9: ...0 4 switches should be in the ON position MSEL 0 4 00010 as shown in Figure 1 2 Figure 1 2 MSEL Default Configuration SW1 is set to low for loading the default factory FPGA configuration For more deta...

Page 10: ...oading speed than the traditional USB Blaster Please note the red edge in the flat cable should be connected to the first pin in JTAG header Figure 1 4 Connect the Terasic USB Blaster II to the JTAG h...

Page 11: ...is required even if there is a power provided through the PCI Express edge connector as shown in Figure 1 6 The 12V DC input can come from the PC power supply if it supports 6 pin PCIe power source W...

Page 12: ...n out of memory error may occur due to the memory limitation of operating system on the host computer The Quartus II golden top project for TR5 Lite is available on the TR5 Lite System CD location Dem...

Page 13: ...1 B Bo oa ar rd d O Ov ve er rv vi ie ew w Figure 2 1 and Figure 2 2 is the top and bottom view of the TR5 Lite development board It depicts the layout of the board and indicates the location of the...

Page 14: ...or programming by USB Blaster the USB Blaster should connect to the JTAG header J3 on the TR5 Lite board The following procedures show how to download a configuration bit stream into the Stratix V GX...

Page 15: ...ring the FPGA Driven by the MAX II CPLD EPM2210 System Controller with the Embedded Blaster CPLD D3 Error Illuminates when the MAX II CPLD EPM2210 System Controller fails to configure the FPGA Driven...

Page 16: ...A Because currently only one mode is supported please set all positions to OFF as shown in Figure 2 3 Figure 2 3 6 Position DIP switch for Configure Mode Selecting Default Factory FPGA Configuration o...

Page 17: ...r ra al l U Us se er r I In np pu ut t O Ou ut tp pu ut t This section describes the user I O interface to the FPGA User Defined Push buttons The TR5 Lite board includes two user defined push buttons...

Page 18: ...nput control Each switch is connected directly to a pin of the Stratix V GX FPGA For 2 position DIP switch when a switch is in the ON position it provides a low logic level to the FPGA as shown in Fig...

Page 19: ...Fa an n C Co on nt tr ro ol l The TR5 Lite is equipped with a temperature sensor MAX1619 which provides temperature sensing and over temperature alert These functions are accomplished by connecting th...

Page 20: ...The development board includes one 50 MHz and two programmable oscillators Figure 2 6 shows the default frequencies of on board all external clocks going to the Stratix V GX FPGA The figures also show...

Page 21: ...Y18 OSC_50_B7A 1 8 V PIN_M9 OSC_50_B7D 1 8 V PIN_J18 OSC_50_B8A 1 8 V PIN_R36 OSC_50_B8D 1 8 V PIN_R25 U2 SFP_REFCLK _p 100 0 MHz LVDS PIN_AK7 10G SFP U46 SFP1G_REFCLK_p 100 0 MHz LVDS PIN_AH6 1G SFP...

Page 22: ...river outputs into a high impedance state 2 5 V PIN_AU23 RS422_DIN Receiver Output The data is send to FPGA PIN_AR24 RS422_DOUT Driver Input The data is sent from FPGA PIN_AV23 RS422_RE_n Receiver Ena...

Page 23: ...Connection between the Flash Max and Stratix V GX FPG Table 2 10 lists the flash pin assignments signal names and functions Table 2 10 Flash Memory Pin Assignments Schematic Signal Names and Functions...

Page 24: ...Address bus 2 5 V PIN_AF31 FSM_D0 Data bus 2 5 V PIN_AF28 FSM_D1 Data bus 2 5 V PIN_AG30 FSM_D2 Data bus 2 5 V PIN_AG25 FSM_D3 Data bus 2 5 V PIN_AK29 FSM_D4 Data bus 2 5 V PIN_BA29 FSM_D5 Data bus 2...

Page 25: ..._AW32 FLASH_OE_n Output enable 2 5 V PIN_AU30 FLASH_WE_n Write enable 2 5 V PIN_AH30 FLASH_ADV_n Address valid 2 5 V PIN_AT29 FLASH_RDY_BSY_n 0 Ready of flash 0 2 5 V PIN_AJ30 FLASH_RDY_BSY_n 0 Ready...

Page 26: ...I PIN_AG11 DDR3A_DQ5 Data 5 SSTL 15 Class I PIN_AH10 DDR3A_DQ6 Data 6 SSTL 15 Class I PIN_AG10 DDR3A_DQ7 Data 7 SSTL 15 Class I PIN_AL12 DDR3A_DQ8 Data 8 SSTL 15 Class I PIN_AN12 DDR3A_DQ9 Data 9 SST...

Page 27: ...e SSTL 15 Class I PIN_BC13 DDR3A_CAS_n Column Address Strobe SSTL 15 Class I PIN_BB11 DDR3A_BA0 Bank Address 0 SSTL 15 Class I PIN_BC16 DDR3A_BA1 Bank Address 1 SSTL 15 Class I PIN_AK12 DDR3A_BA2 Bank...

Page 28: ...Address 0 SSTL 15 Class I PIN_AV13 DDR3B_A1 Address 1 SSTL 15 Class I PIN_AT14 DDR3B_A2 Address 2 SSTL 15 Class I PIN_AT17 DDR3B_A3 Address 3 SSTL 15 Class I PIN_AU12 DDR3B_A4 Address 4 SSTL 15 Class...

Page 29: ...mes relative to the Stratix I GX device in respectively Table 2 13 QDRII SRAM A Pin Assignments Schematic Signal Names and Functions Schematic Signal Name Description I O Standard Stratix IV GX Pin Nu...

Page 30: ...ass I PIN_N14 QDRIIA_D15 Write data bus 15 1 8 V HSTL Class I PIN_P13 QDRIIA_D16 Write data bus 16 1 8 V HSTL Class I PIN_G11 QDRIIA_D17 Write data bus 17 1 8 V HSTL Class I PIN_C10 QDRIIA_Q0 Read Dat...

Page 31: ...5 1 8 V HSTL Class I PIN_C21 QDRIIB_A6 Address bus 6 1 8 V HSTL Class I PIN_D20 QDRIIB_A7 Address bus 7 1 8 V HSTL Class I PIN_A20 QDRIIB_A8 Address bus 8 1 8 V HSTL Class I PIN_D21 QDRIIB_A9 Address...

Page 32: ...1 8 V HSTL Class I PIN_M15 QDRIIB_Q7 Read Data bus 7 1 8 V HSTL Class I PIN_N16 QDRIIB_Q8 Read Data bus 8 1 8 V HSTL Class I PIN_P16 QDRIIB_Q9 Read Data bus 9 1 8 V HSTL Class I PIN_C13 QDRIIB_Q10 Rea...

Page 33: ...15 Address bus 15 1 8 V HSTL Class I PIN_H29 QDRIIC_A16 Address bus 16 1 8 V HSTL Class I PIN_H27 QDRIIC_A17 Address bus 17 1 8 V HSTL Class I PIN_E29 QDRIIC_A18 Address bus 18 1 8 V HSTL Class I PIN_...

Page 34: ..._H23 QDRIIC_Q14 Read Data bus 14 1 8 V HSTL Class I PIN_L24 QDRIIC_Q15 Read Data bus 15 1 8 V HSTL Class I PIN_F25 QDRIIC_Q16 Read Data bus 16 1 8 V HSTL Class I PIN_K24 QDRIIC_Q17 Read Data bus 17 1...

Page 35: ...ID_D0 Write data bus 0 1 8 V HSTL Class I PIN_H31 QDRIID_D1 Write data bus 1 1 8 V HSTL Class I PIN_H30 QDRIID_D2 Write data bus 2 1 8 V HSTL Class I PIN_H32 QDRIID_D3 Write data bus 3 1 8 V HSTL Clas...

Page 36: ...IID_Q15 Read Data bus 15 1 8 V HSTL Class I PIN_B31 QDRIID_Q16 Read Data bus 16 1 8 V HSTL Class I PIN_A31 QDRIID_Q17 Read Data bus 17 1 8 V HSTL Class I PIN_A32 QDRIID_BWS_n0 Byte Write select 0 1 8...

Page 37: ...able 2 17 and Table 2 18 list ists the QSF A and B pin assignments and signal names relative to the Stratix V GX device Table 2 17 SFP A Pin Assignments Schematic Signal Names and Functions Schematic...

Page 38: ...ite development board is designed to fit entirely into a PC motherboard with x8 or x16 PCI Express slot Utilizing built in transceivers on a Stratix V GX device it is able to provide a fully integrate...

Page 39: ...in card transmit bus 1 4 V PCML PIN_AY39 PCIE_TX_n0 Add in card transmit bus 1 4 V PCML PIN_AY40 PCIE_TX_p1 Add in card transmit bus 1 4 V PCML PIN_AV39 PCIE_TX_n1 Add in card transmit bus 1 4 V PCML...

Page 40: ...in card receive bus 1 4 V PCML PIN_AK43 PCIE_RX_n7 Add in card receive bus 1 4 V PCML PIN_AK44 PCIE_REFCLK_p Motherboard reference clock HCSL PIN_AK38 PCIE_REFCLK_n Motherboard reference clock HCSL P...

Page 41: ...tic Signal Names and Functions Schematic Signal Name Description I O Standard Stratix V GX Pin Number SATA_HOST_TX_p0 Differential transmit data output before DC blocking capacitor 1 4 V PCML PIN_AL4...

Page 42: ...generated Quartus II project files include Quartus II Project File qpf Quartus II Setting File qsf Top Level Design File v External PLL Contorller v Synopsis Design Constraints file sdc Pin Assignment...

Page 43: ...roject according to their design requirements When users complete the settings the TR5 Lite System Builder will generate two major files which include top level design file v and the Quartus II settin...

Page 44: ...he detail procedures on how the TR5 Lite System Builder is used Install and launch the TR5 Lite System Builder The TR5 Lite System Builder is located in the directory Tools SystemBuilder in the TR5 Li...

Page 45: ...me as show in Figure 3 3 Project Name Specify the project name as it is automatically assigned to the name of the top level design entity Figure 3 3 The TR5 Lite Project Name System Configuration Unde...

Page 46: ...he DDR3 SDRAM demonstration in Chapter 6 Figure 3 4 System Configuration Group Programmable Oscillator There are two external oscillators on board that provide reference clocks for the following signa...

Page 47: ...g Management The TR5 Lite System Builder also provides functions to restore default setting loading a setting and saving users board configuration file shown in Figure 3 6 Users can save the current b...

Page 48: ...s II Project File 4 Project name qsf Quartus II Setting File 5 Project name sdc Synopsis Design Constraints file for Quartus II 6 Project name htm Pin Assignment Document The SI570 Controller includes...

Page 49: ...TR5 Lite User Manual 49 www terasic com June 20 2018 If dynamic configuration for the oscillator is required users need to modify the code according to users desired behavior...

Page 50: ...ory contents of two interlaced 1Gb 128MB CFI flash device Each flash device has a 16 bit data bus and the two combined flash devices allow for a 32 bit flash memory interface For the factory default c...

Page 51: ...ding to Table 4 Power on the TR5 Lite board or press MAX_RST button if board is already powered on 5 When configuration is completed the green Configure Done LED will light If there is error the red C...

Page 52: ...grammer commands in the flash_program_bashrc_ub2 file as shown in Figure 4 2 Figure 4 2 Disable elf translation and programming If your design includes a NIOS II processor and the NIOS II program is s...

Page 53: ...an refer the Hello example located in the CD folder Demonstrations TR5_Lite_Hello 4 4 4 4 R Re es st to or re e F Fa ac ct to or ry y S Se et tt ti in ng gs s This section describes how to restore the...

Page 54: ...on of the FPGA to Factory Hardware by setting SW1 to low 9 Power on the TR5 Lite and the Configure Done LED should light Except for programming the Flash with the default code TR5_Lite_PFL the batch f...

Page 55: ...Laboratories advanced DSPLL circuitry to provide a low jitter clock at any frequency The Si570 are user programmable to any output frequency from 10 to 945 MHz and select frequencies to 1400 MHz with...

Page 56: ...program the output frequency through the I2C interface using the following procedure 10 Freeze the DCO bit 4 of Register 137 11 Write the new frequency configuration RFREQ HSDIV and N1 to Register 7 1...

Page 57: ...35 Reference Frequrncy RST_REG NewFreq Freeze M Freeze VCADC RECALL 137 Reference Frequrncy Freeze DCO Table 5 2 lists the register settings for some common used frequency Table 5 2 Si570 Register Tab...

Page 58: ...default output frequency is 100 MHZ Users can change the output frequency by the following control pins 1 PR0 and PR1 2 OD0 OD1 and OD2 3 RSTN 4 CE 5 OS0 and OS1 The following table lists the frequen...

Page 59: ...espectively 5 5 2 2 S Si i5 57 70 0 E Ex xa am mp pl le e b by y R RT TL L In this section we will demonstrate how to use the Terasic SI570 Controller implemented in Verilog to control the SI570 progr...

Page 60: ...register value for the i2c_bus_controller based on user desired frequency Once i2c_bus_controller receives this data it will transfer these settings to SI570 via serial clock and data bus using I2C p...

Page 61: ...figuration status 0 Configuration in Progress 1 Configuration Complete I2C_DATA inout I2C Serial Data to from SI570 I2C_CLK output I2C Serial Clock to SI570 To use SI570 Controller the first thing use...

Page 62: ...to be configured or not If it is ready logic high will be outputted and the user needs to send a high level logic to iStart port to enable the SI570 Controller as shown in Figure 5 4 During SI570 conf...

Page 63: ...200 end 3 h1 125Mhz begin new_hs_div 4 b0101 new_n1 8 b0000_1000 fdco 28 h004_E200 end 3 h2 156 25Mhz begin new_hs_div 4 b0100 new_n1 8 b0000_1000 fdco 28 h004_E200 end 3 h3 250Mhz begin new_hs_div 4...

Page 64: ...dco 28 h004_E200 end endcase end Users can get a desired frequency output from si570 by modifying these three parameters new_hs_div new_n1 and fdco Detailed calculation method is in following equation...

Page 65: ...scillator tool See Figure 5 5 mentioned in below link to calculate the values of new_hs_div and new_n1 then the fdco value can be calcuted with above ftdo equation http www silabs com products clockso...

Page 66: ...ject directory TR5_LITE_SI570_Controller Bit stream used TR5_LITE_SI570_Controller sof Demonstration Batch File test bat For USB Blaster test_ub2 bat For USB Blaster II Demo Batch File Folder TR5_LITE...

Page 67: ...0 and CDCM on TR5 Lite Board The demonstration also includes a function to monitor system temperature with the on board temperature sensor System Block Diagram Figure 5 6 shows the system block diagra...

Page 68: ...rogram In temperature test the program will display local temperature and remote temperature The remote temperature is the FPGA temperature and the local temperature the board temperature where the te...

Page 69: ...n Tools Quartus II 11 1 SP2 Nios II Eclipse 11 1 SP2 Demonstration Source Code Quartus II Project directory Nios_BASIC_DEMO Nios II Eclipse Nios_BASIC_DEMO Software Nios II IDE Project Compilation Bef...

Page 70: ...is downloaded and executed successfully a prompt message will be displayed in nios2 terminal For temperature test please input key 0 and press Enter in the nios terminal as shown in Figure 5 8 For pro...

Page 71: ...TR5 Lite User Manual 71 www terasic com June 20 2018 Figure 5 9 CDCM 61004 Demo Figure 5 10 Si570 Demo...

Page 72: ...ne bank of DDR3 SDRAM with Nios II Note 64 Bit Quartus 11 1 SP1 or later is strongly recommended for compiling these projects 6 6 1 1 Q QD DR RI II I S SR RA AM M T Te es st t QDR II QDR II SRAM devic...

Page 73: ...II SRAM controllers are sharing the FPGA resources OCT PLL and DLL and the QDRII SRAM C is configured as the master to share the resource to the other three slave QDRII SRAM A B D RW_test modules read...

Page 74: ...us menu Tools TCL Scripts Design Tools Quartus II v13 1 Demonstration Source Code Project directory TR5_Lite_QDRIIx4_Test Bit stream used TR5_Lite_QDRIIx4_Test sof Demonstration Batch File Demo Batch...

Page 75: ...gnals for a repeat test Table 6 1 LED Indicators NAME Description LED0 QDRII SRAM A test result LED1 QDRII SRAM B test result LED2 QDRII SRAM C test result LED3 QDRII SRAM D test result 6 6 2 2 D DD D...

Page 76: ...ted data the same sequence as the write data BUTTON0 will trigger test control signals for the two DDR3 and the LEDs will indicate the test results according to Table 6 2 Altera DDR3 SDRAM Controller...

Page 77: ...cable or USB Blaster II cable to the TR5 Lite board and host PC Install the USB Blaster driver if necessary Power on the TR5 Lite board Execute the demo batch file TR5_Lite_DDR3x2_Test bat or TR5_Lit...

Page 78: ...DR3 memory access in QSYS We describe how the Altera s DDR3 SDRAM Controller with UniPHY IP is used to access a DDR3 SDRAM and how the Nios II processor is used to read and write the SDRAM for hardwar...

Page 79: ...ta verification The program will show progress in JTAG Terminal when writing reading data to from the SDRAM When verification process is completed the result is displayed in the JTAG Terminal Altera D...

Page 80: ...artus II compilation Design Tools Quartus II 13 1 Nios II Eclipse 13 1 Demonstration Source Code Quartus Project directory Nios_DDR3 Nios II Eclipse Nios_DDR3 Software Nios II Project Compilation Befo...

Page 81: ...nder the batch file folder Nios_DDR3 demo_batch DDR3_A_667MHZ or Nios_DDR3 demo_batch DDR3_B_667MHZ After Nios II program is downloaded and executed successfully a prompt message will be displayed in...

Page 82: ...nal loopback method The following transceiver channels can be verified with different data rates 10 3125 Gbps SPF A SPF B 6 0 Gbps SATA Host 8 0 Gbps PCIe Channel 0 7 7 7 2 2 L Lo oo op pb ba ac ck k...

Page 83: ...igure 7 2 shows the SATA loopback fixture Figure 7 2 SATA Loopback Fixture 176H174HFigure 7 3 shows the Terasic PCIe loopback fixture Figure 7 3 PCIe Loopback Fixture 177H175HFigure 7 4 shows the FPGA...

Page 84: ...if the SATA transceivers will be tested 5 Plug in the PCIe loopback fixture if PCIe transceivers will be tested Also make sure PCIe Mode SW7 is switched to x8 mode 6 Connect your FPGA board to your P...

Page 85: ...TR5 Lite User Manual 85 www terasic com June 20 2018 Figure 7 5 Transceiver Loopback Test in Progress...

Page 86: ...176 Sec 2 Gongdao 5th Rd East Dist HsinChu City 30070 Taiwan 30070 Email support terasic com Web www terasic com TR5 Lite Web tr5 lite terasic com R Re ev vi is si io on n H Hi is st to or ry y Date...

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