Terasic TR-5 Lite FPGA, User Manual

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TR5-Lite User Manual 22 www.terasic.com
June 20, 2018
Figure 2-7 Block Diagram of RS-422
Table 2-9 lists the RS-422 pin assignments, signal names and functions.
Table 2-9 RS-422 Pin Assignments, Schematic Signal Names, and Functions
Schematic
Signal Name
Description I/O Standard
Stratix V GX Pin
Number
RS422_DE
Driver Enable. A high on DE enables
the driver. A low input will force the
driver outputs into a high impedance
state.
2.5-V
PIN_AU23
RS422_DIN
Receiver Output. The data is send to
FPGA.
PIN_AR24
RS422_DOUT
Driver Input. The data is sent from
FPGA.
PIN_AV23
RS422_RE_n
Receiver Enable. A low enables the
receiver. A high input forces the
receiver output into a high impedance
state.
PIN_AL24
RS422_TE
Internal Termination Resistance
Enable. A high input will connect a
termination resistor (120
Ω typical)
between pins A and B.
PIN_AL23
2
2
.
.
7
7
F
F
L
L
A
A
S
S
H
H
M
M
e
e
m
m
o
o
r
r
y
y
The development board has two 1Gb CFI-compatible synchronous flash devices for non-volatile