DE3 User Manual
47
Figure 4.8. The error message box of an incorrect connection
Project Generation
When users press the Generate button, the DE3 System Builder will generate the
corresponding Quartus II files and documents as listed in the
Table 4-1
:
Table 4-1. The files generated by DE3 System Builder
No.
Filename
Description
1
<Board name>.v
Top level verilog file for Quartus II
2
IOV_<IO Group voltage level>.v
Encrypted
Power
Configuration
Controller IP
3
<Board name>.qpf
Quartus II Project File
4
<Board name>.qsf
Quartus II Setting File
5
<Board name>.sdc
Synopsis Design Constraints file for
Quartus II
6
<Board name>.htm
Pin Assignment Document
Users can use Quartus II software to add custom logic into the project and compile the
project to generate the SRAM Object File (.sof).
In addition, the Encrypted Power Configuration Controller IP is used to control the
V
CCIO
level of the I/O Groups. This IP file is included in the Quartus II top-level file as
listed in below:
Summary of Contents for Altera DE3
Page 1: ...Altera DE3 Board ...
Page 67: ...DE3 User Manual 64 Figure 5 5 Plug USB Devices into DE3 Figure 5 6 Display Device Information ...
Page 75: ...DE3 User Manual 72 Figure 5 14 Display SD Card Information for the SD Card Demonstration ...
Page 79: ...DE3 User Manual 76 Figure 5 19 Parameter Settings in DDR2 Controller ...
Page 114: ...DE3 User Manual 111 Figure D 5 The reported message of the invalid I O pins ...
