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DE3 User Manual

Chapter 5

Examples of Advanced Demonstration

This chapter provides a number of examples of advanced circuits implemented on the DE3 board.

These circuits demonstrate the major features onboard, such as its SD card, USB host and device,

and DDR2. For each demonstration the Stratix III FPGA configuration file is provided, as well as

full source code in Verilog HDL code. All of the associated files can be found in the

DE3_demonstrations folder from the DE3 System CD. There are four sub-folders named 340, 260,

150ES, and 150 under the directory of DE3_demonstrations. The numbers correspond to the Stratix

III FPGA EP3SL340, EP3E260, EP3S150ES, and EP3S150 on DE3 board. For each of

demonstrations described in the following sections, we give the name of the project directory for its

files, which are sub-directories of the DE3_demonstrations folder.

5.1

USB Host

USB is a well-known communication standard used in many peripherals. The DE3 board provides a

complete USB solution for both host and device applications. In this demonstration, USB host

functions are implemented for USB mass-storage and Human-interface devices (HIDs) USB-Mouse.

The drivers of the above applications are implemented in NIOS II C code. All high-speed,

full-speed, and low-speed devices are supported in this demonstration.

Figure 5.1

shows the hardware system block diagram of this demonstration. The system requires a

50 MHz clock provided from the board. The PLL generates a 100 MHz clock for NIOS II processor

and high-speed controllers, and generate 10 MHz clock for low-speed peripherals, such as buttons.

A custom-defined SOPC ISP1761 controller, developed by TERASIC, is used to connect the

ISP1761 USB chip and NIOS II processor. Based on this controller, NIOS II processor can access

the register, memory, and interrupts of the USB chip. A PIO pin, named usb_reset_n, is connected to

the USB for performing hardware reset of the USB chip. The NIOS II program is stored in the

On-Chip Memory.

Summary of Contents for Altera DE3

Page 1: ...Altera DE3 Board ...

Page 2: ...g the USB OTG 22 2 10 Using the SD Card 23 2 11 LED Indicators 24 2 12 Clock Circuitry 24 2 13 Using the Temperature Sensor 27 Chapter 3 Control Panel 28 3 1 Control Panel Setup 28 3 2 Controlling the LEDs and 7 Segment Displays 31 3 3 SWITCH BUTTON 33 3 4 Memory Controller 33 3 5 USB2 0 OTG 35 3 6 SD CARD 36 3 7 Temperature Monitor 37 3 8 I O Group 38 3 9 Overall Structure of the DE3 Control Pane...

Page 3: ...3 Appendix A Pin connections between components and FPGA on the DE3 board 80 Appendix B Pin Compatible List for HSTC and HSMC Connector 98 Appendix C Programming the Serial Configuration Device 102 Appendix D DE3_HSTC Utility 108 Appendix E LVDS Termination Resistors 112 Additional Information 114 Getting Help 114 Revision History 114 ...

Page 4: ...ess into practice while the SD card socket provides the realization of data storage extension In addition the DE3 board has an innovative stackable mechanism which allows users to assemble DE3 boards into a powerful system as shown in Figure 1 1 The DE3 can also connect with multiple daughter boards designed by Terasic in stock Figure 1 1 The stackable mechanism of the DE3 board 1 2 Layout and Com...

Page 5: ...C Bottom Side Enable 8 RGB LEDs Expansion Header 1 4 Push Button Switches USB Blaster Power ON OFF Switch Power Supply Connector USB Device SD Card Slot USB Device USB Host Device SMA PLL Clock Out Altera Stratix III 3SL340 DE3 340 or 3SL260 DE3 260 or 3SL150 DE3 150 Reconfigure Switch CPU RESET Switch 8 Position Dip Switch HSTC Connector C HSTC Connector D HSTC Connector B HSTC Connector A 12V Fa...

Page 6: ...lowing hardware is implemented on the DE3 board Altera Stratix III FPGA device 3SL340 3SE260 3SL150 FPGA configuration interface Built in USB Blaster circuit for programming and user API control Altera Serial Configuration device EPCS128 EPCS64 Expansion Interface 8 HSTC connectors Two 40 pin Expansion Headers Memory Interface DDR2 SO DIMM socket SD Card socket ...

Page 7: ...PLL clock output Other interface 1 USB Host Slave controller 1 three ports USB Host Device controller 1 temperature sensor chip for FPGA temperature measurement 1 3 Block Diagram of the DE3 Board Figure 1 4 shows the block diagram of the DE3 board To provide maximum flexibility for the users all key components are connected with the Stratix III FPGA device Thus users can configure the FPGA to impl...

Page 8: ... Clock IN x5 Clock OUT x5 HOST CON DEVICE CON GPIO 1 x80 PLL OUT CLOCK IN 50 MHz OSC OSC x6 EPM240 JTAG x4 USB CON 7 Seg x 16 DIP Switch x 8 I2 C x2 I2 C x2 I2 C x2 I2 C x2 JVC x4 Select and Power ON I2 C x2 Stratix III EP3SL150F1152 EP3SL340F1152 EP3SE260F1152 Adjustable Voltage Signal 3 3V Bank I O Voltage 3 3V Signal SD Card Socket Button Switch x4 Color LED x 24 Slider Switch x4 SD Card x 4 x1...

Page 9: ...8 bit Multipliers blocks 12 phase locked loops PLLs EP3SL150 142 000 logic elements LEs 6 390K Total Memory Kbits 384 18x18 bit Multipliers blocks 8 phase locked loops PLLs Serial Configuration device and USB Blaster circuit Altera s EPCS128 EPCS64 Serial Configuration device On board USB Blaster for programming and user API control Support JTAG mode DDR2 SO DIMM socket Up to 4GB capacity Share th...

Page 10: ...cification Rev 2 0 Support data transfer at high speed full speed and low speed Support both USB host and device Three USB ports one type mini AB for host device and two type A for host Support Nios II with the Terasic driver Support Programmed I O PIO and Direct Memory Access DMA Eight 180 pin High Speed Terasic Connectors HSTC expansion headers 4 male and 4 female connectors are on the top and t...

Page 11: ... the DE3 Board 8 Programming the FPGA Device on the DE3 Board 2 1 Configuring the FPGA and Serial Configuration Device Programming the FPGA device The DE3 board has a built in USB Blaster circuit which allows users to program the FPGA device using USB cable and Quartus II programmer in JTAG mode Current configuration will be lost when the power is turned off To download a configuration bit stream ...

Page 12: ...ration device via the JTAG interface The FPGA based SFL is a soft intellectual property IP core within the FPGA that bridges the JTAG and flash interfaces The SFL mega function is available from Quartus II software Figure 2 2 shows the programming method when adopting a SFL solution Please refer to Appendix C Programming the Serial Configuration device for the basic programming instruction on the ...

Page 13: ...ntrol the JTAG interface signals of bottom HSTC connectors Table 2 1 indicates the detailed configurations of SW6 When the bottom connector is connected with other DE3 board or an daughter board users need to configure the SW6 to connect the JTAG chain to other board accordingly Figure 2 5 shows there are two DE3 boards stacked and the JTAG chain is established through HSTA connector A as shown in...

Page 14: ...Bypassed HSTC Connector C Bypassed HSTC Connector D Bypassed 2 3 4 1 Figure 2 3 JTAG chain for a standalone DE3 board TDO TDI TDI TDO HSTC Connector A Top TDI TDO TDO TDI USB Blaster Circuit USB Cable Host PC Stratix III FPGA Daughter Board DE3 Board OFF OFF OFF OFF SW6 Figure 2 4 JTAG chain for a daughter board connected with DE3 board via top HSTC connector A ...

Page 15: ...A TDO TDI HSTC Connector A Bottom TDI TDO TDO TDI USB Blaster Circuit USB Cable Host PC TDO TDI HSTC Connector A Top TDI TDO TDO TDI USB Blaster Circuit SW6 1 2 3 4 ON OFF DE3 Board 1 DE3 Board 2 OFF OFF Stratix III FPGA Stratix III FPGA SW6 1 2 3 4 OFF OFF OFF OFF Figure 2 6 JTAG chain for two stacked DE3 boards ...

Page 16: ...tton depressed button depressed button depressed button depressed Before Before Before Before Debouncing Debouncing Debouncing Debouncing Schmitt Triger Schmitt Triger Schmitt Triger Schmitt Triger Debounced Debounced Debounced Debounced Push Push Push Push button released button released button released button released Figure 2 7 Switch debouncing Slide Switches and DIP Switch There are also four...

Page 17: ...splay is identified by an index listed from 0 to 6 with the positions given in Figure 2 9 In addition the decimal point is identified as DP Table A 5 shows the mapping of the FPGA pin assignments to the 7 segment displays 3 7 9 8 5 10 4 2 HEX1_D0 M1 L1 L2 V4 P3 N4 Y11 W12 Y5 Y6 V3 HEX1 HEX0 HEX1_D1 HEX1_D2 HEX1_D3 HEX1_D4 HEX1_D5 HEX1_D6 HEX1_DP HEX0_D0 HEX0_D1 HEX0_D2 HEX0_D3 HEX0_D4 HEX0_D5 HEX0...

Page 18: ...Such tool is intended to generate a top level Quartus II project which includes the power controller IP After the FPGA is programmed the power controller IP will control the VCCIO control circuit to provide desired VCCIO and VCCPD level to the FPGA according to I O standard selected by users as indicated in Figure 2 10 With this feature users can not only confirm if the VCCIO level meets the desig...

Page 19: ... for the status of the LED indicator For I O Group A For I O Group D For I O Group C For I O Group B Power ON OFF Indicator Figure 2 11 The Voltage Level Indicator for the I O Groups Table 2 3 The LEDs indicates the VCCIO voltage level of each IO Group LED VCCIO Vx1 1 Vx0 1 OK 3 3V Light ON Light ON Light ON 2 5V Light ON Light OFF Light ON 1 8V Light OFF Light ON Light ON 1 5V Light OFF Light OFF...

Page 20: ...S inout On bank 2 and 3 the I O pins used in differential transmitter channels support emulated LVDS via a termination resistor and the differential receiver channels support true LVDS as shown in Figure 2 12 In addition there is a software utility named DE3_HSTC which can perform the connection test between the I O pins of the HSTC connector and Stratix III FPGA The detailed information about thi...

Page 21: ...HSTCA_CLKIN_n0 HSTCA_CLKIN_p0 HSTCA_RX_n0 HSTCA_RX_p0 HSTCA_RX_n1 HSTCA_RX_p1 HSTCA_RX_n2 HSTCA_RX_p2 HSTCA_RX_n3 HSTCA_RX_p3 HSTCA_RX_n4 HSTCA_RX_p4 HSTCA_RX_n5 HSTCA_RX_p5 HSTCA_RX_n6 HSTCA_RX_p6 HSTCA_RX_n7 HSTCA_RX_p7 HSTCA_RX_n8 HSTCA_RX_p8 6 6 8 8 10 10 12 12 14 14 16 16 18 18 20 20 22 22 24 24 26 26 28 28 30 30 32 32 34 34 36 36 38 38 40 40 42 42 44 44 46 46 48 48 50 50 52 52 54 54 56 56 58...

Page 22: ...ed at the same time Power Supply The HSTC connector provides 12 5 and 3 3 volt for power supply purpose There are also two power input pin named B HSTC Group _VTT and B HSTC Group _VREF which are connected to the input reference voltage VREF and termination voltage pin VTT of the Stratix III FPGA respectively Finally Table A 6 to Table A 11 shows the connections between the HSTC connectors and the...

Page 23: ...or are only used to establish connection for stacking purposes 2 7 Using the GPIO Expansion Headers The DE3 Board provides two 40 pin expansion headers as shown in Figure 2 14 Each header has 36 pins connected to the Stratix III FPGA and the two headers share the same I O pins with HSTC connector A The other 4 pins provide DC 5V VCC5 DC 3 3V VCC33 and two GND pins Among these 36 I O pins there are...

Page 24: ...1_D16 GPIO1_D18 GPIO1_D20 3 3V GPIO1_D22 GPIO1_D24 GPIO1_D26 GPIO1_D28 GPIO1_D30 GPIO1_D0 GPIO1_D1 GPIO1_D3 GPIO1_D5 GPIO1_D7 GND GPIO1_D9 GPIO1_D11 GPIO1_D13 GPIO1_D14 GPIO1_D15 GPIO1_D17 GPIO1_D19 GPIO1_D21 GND GPIO1_D23 GPIO1_D25 GPIO1_D27 GPIO1_D29 GPIO1_D31 J14 GPIO 1 Figure 2 14 Pin distribution of the GPIO expansion headers 1 3 19 AD19 AE32 AE31 AE18 GPIO 0 GPIO 1 CLKOUTn0 CLKOUTp0 CLKINn0 ...

Page 25: ...DR2_SDA HSTC B DDR2_CS_n 0 1 DDR2_SA 0 1 Figure 2 16 Connections between the DDR2 and Stratix III FPGA 2 9 Using the USB OTG The DE3 board provides both USB host and device interfaces using the Philips ISP1761ET single chip USB controller The host and device controllers are compliant with the Universal Serial Bus Specification Rev 2 0 supporting data transfer at high speed 480 Mbit s full speed 12...

Page 26: ...from the manufacturer s web site or in the Datasheet USB folder of the DE3 System CD Two complete examples for host and device applications each can be found in Sections 5 1and 5 2 These demonstrations provide software drivers for the Nios II processor Table 2 4 The default host or peripheral setting for port 1 J15 of the ISP1761ET JP1 setting Connectors Open Port1 set to peripheral Close Port 1 s...

Page 27: ...r C top J5 is connected with an extended board LINKD Light on when HSTC connector D top J7 is connected with an extended board OVT Light on when the temperature value of the FPGA is higher than the threshold value setting in the temperature sensor USB3 USB2 USB1 Power LED indicators for USB port3 J17 port2 J16 and port1 J1 Each LED will be on as soon as the port power of the respective port is ena...

Page 28: ...ut of Stratix III FPGA includes HSTC connectors GPIO expansion headers SMA connector and SD card socket as shown in Figure 2 19 The associated pin assignments for clock buffer and SMA connectors to FPGA I O pins are shown in Table A 17 ...

Page 29: ..._RX_L11p DIFFIO_TX_L12p Level Shift Level Shift Level Shift VCCIO Bank 1C CLK1p VCCIO Bank 5C Bank 6C CLK8p CLK10p EXT_CLK SMA CLK_OUT PLL_R3_FB_CLKOUT0p SMA 24MHz Oscillator High Speed Clock Buffer PLL_T1_CLKOUT3 PLL_T1_CLKOUT0n PLL_T1_CLKOUT0p PLL_T2_CLKOUT3 PLL_T2_CLKOUT0n PLL_T2_CLKOUT0p PLL_B2_CLKOUT3 PLL_B2_CLKOUT0n PLL_B2_CLKOUT0p PLL_B1_CLKOUT3 PLL_B1_CLKOUT0n PLL_B1_CLKOUT0p CLKOUT_n0 CLK...

Page 30: ...et to 0011000 There is an option of connecting a 2 pin 12V fan to JP2 for cooling purpose The pin near the HSTC connector C is for 12V the other one is used for GND When the temperature of the FPGA device is over the threshold value set by users the fan will be turned on The pin assignments for the associated interface are listed in Table A 18 Finally the detailed information of the temperature se...

Page 31: ...l exe will auto detect the FPGA and download the control codes the sof and elf file to the Stratix III device through USB Blaster port To activate the Control Panel perform the following steps 1 Make sure Quartus II and NIOS II are installed successfully on your PC 2 Connect the supplied USB cable to the USB Blaster port and the supplied power cord to J18 Turn the power switch ON as shown in Figur...

Page 32: ...DE3 User Manual 29 Figure 3 1 Setup of USB Blaster cable and power cord Figure 3 2 Download sof and elf files to the DE3 board ...

Page 33: ... board and USB Blaster is not established or the DE3 board is not powered on before running the DE3_control_panel exe the Control Panel will fail to detect the FPGA and a warning message window will pop up as shown in Figure 3 4 Figure 3 4 The DE3 Control Panel fails to download sof file ...

Page 34: ...ANK POWER Power Off Write Read Figure 3 5 The DE3 Control Panel concept The DE3 Control Panel can be used to light up LEDs change the values displayed on 7 segment displays monitoring buttons switches status read write the serial configuration devices EPCS128 access DDR2 SO DIMM memory read the information of SD Card and setup the VCCIO level of the I O Groups 3 2 Controlling the LEDs and 7 Segmen...

Page 35: ...nual 32 Figure 3 6 Controlling LEDs Figure 3 7 shows the interface of the 7 SEG and how to select desired patterns The status of the 7 SEG patterns will be updated immediately Figure 3 7 Controlling 7 SEG display ...

Page 36: ... is accessed Click on the Memory tab to reach the tab window shown in Figure 3 9 A 16 bit string can be written into the DDR2 SO DIMM memory by three steps namely specifying the address of the desired location entering the data to be written and pressing the Write button Contents of the location can be read by pressing the Read button Figure 3 10 depicts the result of writing the hexadecimal value...

Page 37: ...nner The Sequential Read function is used to read the contents of the serial configuration device and place them into a file as follows 1 Specify the starting address in the Address box 2 Specify the number of bytes to be copied into a file in the Length box If the entire contents of the serial configuration device are to be copied then place a check mark in the Entire Memory box 3 Press Load Memo...

Page 38: ...the USB tab to reach the window in Figure 3 11 The function is designed to monitor the status of USB Hub in real time Plug a USB device to any USB port of FPGA board and both the device type and speed will be displayed on the control window Figure 3 11 shows a low speed HID USB Mouse is plugged into port 3 ...

Page 39: ...to read the identification and specification of SD Card Single bit SD MODE is used to access the SD Card This function can be used to verify the functionality of SD CARD interface To gather the information simply insert a SD Card to the FPGA board and press the Read button The SD CARD identification and specification will be displayed on the control window ...

Page 40: ...emperatures of Stratix III and DE3 board are shown on the right hand side of the Control Panel When the temperature of Stratix III exceeds the Maximum setting of Over Temperature or Alert a warning message will be shown on the Control Panel Click Read button to get current settings for Over temperature and Alert Users can enter the maximum and minimum temperatures for Over temperature or Alert as ...

Page 41: ...O Group Choose the I O Group tab to reach the window shown in Figure 3 14 The function is designed to read write and control the VCCIO level of all I O Groups of the DE3 board Click the Read button to enter the window shown in Figure 3 15 Current VCCIO level of all I O Groups will be displayed ...

Page 42: ...DE3 User Manual 39 Figure 3 14 Accessing the power status of all I O Groups Figure 3 15 Reading the VCCIO level of all I O Groups ...

Page 43: ...t set it up first as explained in Section 3 1 Figure 3 16 depicts the structure of the Control Panel Each input output device is controlled by the NIOS II Processor instantiated in the FPGA chip The communication with the PC is done via the USB Blaster link The NIOS II interprets the commands sent from the PC and performs the appropriate actions Figure 3 16 The block diagram of the DE3 control pan...

Page 44: ...ovide error checking rules to prevent users from making the following common mistakes 1 Board damaged for wrong pin bank voltage assignment 2 Board malfunction caused by wrong device connections or missing pin counts for connected ends 3 Performance dropped because of improper pin assignments 4 2 General Design Flow This section will introduce the general design flow to build a project for the DE3...

Page 45: ...pin Next users must be aware that they can never modify encrypted power configuration controller file User s own design should be included within top level deign file Finally Quartus II programmer must be used to download SOF file to DE3 board using JTAG interface Start Launch DE3 System Builder Create New DE3 System Builder Project QPF QSF V HTML SDC Generate Quartuss II Project and Document Laun...

Page 46: ... IP is set in the Quartus II software Please refer to the section Add the License File for Terasic Power Controller IP in the document named Getting start with Altera DE3 board for more information on how to import a license file Execute DE3_System_Builder exe on the host computer The DE3 System Builder user interface will appear as shown in Figure 4 2 Figure 4 2 The DE3 System Builder window Add ...

Page 47: ...E3 board as described below Figure 4 3 The DE3 Configuration window Board Name The board name will be set as the Quartus II project name when it is created by DE3 System Builder FPGA Type The FPGA device on DE3 board may be EP3SL150 or EP3SH340 Users need to select the FPGA device and speed grade accordingly User I O Components Users can enable or disable the User I O Component from this field If ...

Page 48: ...on will indicate the VCCIO level for current I O standard setting of the four I O Croups The status is same as the LEDs on the DE3 board Please refer to Section 2 4 for details Connection Between Two Connectors When users add a DE3 board and daughter board in the System configuration field it is necessary to establish the connection in between The port name port connection rules input output and t...

Page 49: ... 4 6 Step 3 of establishing a connection iv Redo the steps i to iii will remove an established connection as shown in Figure 4 7 Figure 4 7 The step for removing a connection between two connectors Warning message of an incorrect connection If users try to establish a connection between two different types and I O standard of connectors a warning message box will pop up as shown in Figure 4 8 ...

Page 50: ...OV_ IO Group voltage level v Encrypted Power Configuration Controller IP 3 Board name qpf Quartus II Project File 4 Board name qsf Quartus II Setting File 5 Board name sdc Synopsis Design Constraints file for Quartus II 6 Board name htm Pin Assignment Document Users can use Quartus II software to add custom logic into the project and compile the project to generate the SRAM Object File sof In addi...

Page 51: ...the I O Group For example the filename IOV_A3V3_B1V8_C3V3_D2V5 v means that the VCCIO voltage level of the I O Group A B C and D are 3 3V 1 8V 3 3V and 2 5V respectively Project Open Close Save Save As The DE3 System also provides functions to open close and save user s system configuration file Users can save the current system configuration information into a scf file and load it to the DE3 Syst...

Page 52: ...I O interface After the above is completed a DE3 Configuration window will pop up Please follow Figure 4 10 to modify the configuration as described below i Change the Board Name from DE3 to MY_FISRT_DE3_PROJECT ii Make sure the FPGA type is same as user s DE3 board iii Disable all the components and IO Group except the LED iv Click OK button to complete the configuration Figure 4 10 The DE3 Confi...

Page 53: ...check the status of the LED0 LED7 on the DE3 board The LEDs should be lightening in blue 4 5 Connect TERASIC Daughter Boards to a DE3 Board This section describes how to create a project when connecting a DE3 board with a Terasic daughter board via the DE3 System Builder The DE3 System Builder will provide the following features The I O standard and the pin names of the HSTC connector pins will be...

Page 54: ...er s DE3 board iii Disable all the components and IO Group except for IO Group C iv Click OK button to complete the configuration MTDB HSTC Connector D HSTC Connector A HSTC Connector B HSTC Connector C Figure 4 11 The hardware connection for the demonstration Figure 4 12 The Configuration for the example ...

Page 55: ...guration field of the DE3 System Builder 5 Establish a connection between DE3 board and MTDB board i In the System Configuration field establish a connection from the HSTCC Male connector of the DE3 board and the MTDB board shown in Figure 4 14 Figure 4 14 Establish a connection between the DE3 board and the MTDB board ii After the connection is established the DE3 System Builder will change the I...

Page 56: ...board iv Compile the project to generate the SRAM Object files sof 8 Configure the FPGA device i If the generated project is configured to FPGA device for the first time please make sure all the boards are removed from the DE3 board before powering up ii Configure the FPGA device via the USB cable iii Check the status of I O Group indication LEDs to see if the voltage level for I O Group is correc...

Page 57: ...ure the FPGA Type is the same as user s DE3 board iii Click OK button to complete the configuration 4 Add another DE3 board into system i Repeat the step2 to step3 to add another DE3 board ii Change the Board Name from DE3 to DE3_BOTTOM iii Change all the type of I O Groups to HSTC iv Make sure the I O standard of all I O Groups is same as the other DE3 board 5 Establish connections between two DE...

Page 58: ...DE3 User Manual 55 Figure 4 17 The DE3 Configuration window Figure 4 18 The connection between the two DE3 boards ...

Page 59: ...he top level file and compile the project to generate the SOF file 8 Configure the FPGA device 4 7 Connect a Custom Made Daughter Board to the DE3 Board If users want to connect a custom made daughter board to the DE3 board the most important thing is to make sure that both DE3 board and the custom daughter board support the same I O standard The following example shows how to connect a custom dau...

Page 60: ...o generate the SRAM object files sof 6 Configure the FPGA device i If the generated project is configured to FPGA device for the first time please make sure all the boards are removed from the DE3 board before powering up ii Configure the FPGA device via the USB cable iii Check the status of I O Group indication LEDs to see if the voltage level of I O Group is correct iv Power off the DE3 board an...

Page 61: ...ell known communication standard used in many peripherals The DE3 board provides a complete USB solution for both host and device applications In this demonstration USB host functions are implemented for USB mass storage and Human interface devices HIDs USB Mouse The drivers of the above applications are implemented in NIOS II C code All high speed full speed and low speed devices are supported in...

Page 62: ...rol and bulk transfers USB Host controller block implements control functions for ISP1761 Host Controller USB protocol block implements USB protocol including USB Hub protocol The USB Mouse Class Driver implements functions to communicate with HID USB Mouse The USB mass storage Class Driver implements functions to communicate with Bulk Only Transport USB mass storage based on USB Floppy Interface ...

Page 63: ...on in standard output In this demonstration NIOS II uses PIO mode to access the internal memory of ISP1761 For high throughput application DMA implementation and interrupt can enhance data transfer rate significantly FAT File System USB mass storage Class Driver NIOS II PIO USB Mouse Class Driver ISP 1761 HAL USB Host Controller USB Protocol Main Figure 5 2 Software Stack of the USB Host Demonstra...

Page 64: ...rage Driver Instance Yes No Associated Mouse Instance Exists Yes No No Init Host Controller Start USB mass storage Attached Figure 5 3 Software workflow of the USB Host Demonstration Demonstration Source Code Quartus II Project directory DE3_USB FPGA Bit Stream DE3_USB sof NIOS II Workspace DE3_USB Software Project_Usb_Host The NIOS II source code list is shown in Figure 5 4 Users can modify teras...

Page 65: ...st Controller USB Protocol Main Figure 5 4 Source Code List of the USB Host Demonstration Demonstration Batch File Demo Batch File Folder DE3_USB Demo_Batch usb_host The demo batch file folders include the following files Batch File de3_usb_host bat de3_usb_host_bashrc FPAG Configuration File DE3_USB sof NIOS II Program usb_host elf ...

Page 66: ...e device or HID USB Mouse into the USB ports in DE3 as shown in Figure 5 5 The device information will be displayed in nios2 terminal as shown in Figure 5 6 Reference ISP1761 Hi Speed Universal Bus On The Go controller Rev 04 5 March 2007 Universal Serial Bus Specification Revision 2 0 April 27 2000 Enhanced Host Controller Interface Specification for Universal Serial Bus Revision 1 0 March 12 200...

Page 67: ...DE3 User Manual 64 Figure 5 5 Plug USB Devices into DE3 Figure 5 6 Display Device Information ...

Page 68: ...pes are defined in the header file io h The ISP 1761 HAL block implements functions to access internal control data registers of the USB chip ISP 1761 USB Peripheral controller block implements control functions for ISP1761 Peripheral Controller USB protocol block implements USB protocol USB Bulk Driver implements a device driver to provide two bulk end points namely Bulk In and Bulk Out Main prog...

Page 69: ...ctory DE3_USB FPGA Bit Stream DE3_USB sof NIOS II Workspace DE3_USB Software Project_Usb_Device The NIOS II source code list is shown in Figure 5 9 Users can modify terasic_debug h to configure the debug message Note that any debug message may affect the USB performance or even cause malfunction in this demonstration ...

Page 70: ...mo Batch File Folder DE3_USB demo_batch usb_device The demo batch file includes the following files Batch File de3_usb_device bat de3_usb_device_bashrc FPAG Configure File DE3_USB sof NIOS II Program usb_device elf USB Driver for Windows XP terasic_usb sys and terasic_usb inf USB Test Program for Windows XP DE3_UsbControl exe Demonstration Setup It is suggested to run this demonstration under Wind...

Page 71: ...og will pop up to request a USB driver to be installed The required driver is available in the demo batch folder DE3_USB demo_batch usb_device Launch DE3_UsbControl exe under the batch file folder DE3_USB demo_batch usb_device Click Connect in DE3_UsbControl window After connection established the button status in DE3 will be updated to the program interface and users can start to configure the LE...

Page 72: ...are all implemented by NIOS II software The software is stored in the on chip memory FPGA SOPC PIO Controller System Interconnect Fabric NIOS II JTAG Timer On Chip Memory PIO Controller Button LED 50MHz PLL PIO Controller SD Card Socket Figure 5 11 Block Diagram of the SD Card Demonstration Figure 5 12 shows the software stack of this demonstration The NIOS PIO block provides basic IO functions to...

Page 73: ...s the FAT file system it will turn on the green LED On the other hand it will turn on the red LED if it fails to parse the FAT file system or if there is no SD card found in the SD Card socket of the DE3 board If users press BUTTON3 of the DE3 board the program will perform above process again Main FAT File System SD CARD NIOS II PIO Figure 5 12 Software Stack of the SD Card Demonstration Demonstr...

Page 74: ...h file folder DE3_SDCARD demo_batch After NIOS II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal Copy test files to the root directory of the SD Card Insert the SD card into the SD Card socket of DE3 as shown in Figure 5 13 Press Button3 of the DE3 board to start reading SD Card The program will display SD Card information as shown in Figure 5 ...

Page 75: ...DE3 User Manual 72 Figure 5 14 Display SD Card Information for the SD Card Demonstration ...

Page 76: ...PC builder limitation For none SOPC project users can change the DDR2 IP setting to support higher capacity of SDRAM Figure 5 15 shows the system block diagram of this demonstration The system requires a 50 MHz clock provided from the board The DDR2 controller is configured as a 256M Bytes DDR2 533 controller The DDR2 IP generates one 266 667 MHZ clock as SDRAM s data clock and one half rate syste...

Page 77: ...verification process is completed the result is displayed in the JTAG Terminal Altera DDR2 SDRAM High Performance Controller To use Altera DDR2 contrroler users need to perform three major steps 1 Create correct pin assignment for DDR2 2 Setup correct parameters in DDR2 controller dialog 3 Execute TCL files generated by DDR2 IP under your quartus project 1 Pin Assignments DE3_System builder can he...

Page 78: ...s for DDR2 controller The controller is configured as DDR2 SDRAM 266 667 MHZ 64 bits width Un buffered DIMM CAS 5 0 1 DIMM To see the detail parameter information as showing in Figure 5 19 users can click modify parameters button User can change the SDRAM capacity in this setting dialog Figure 5 18 Memory Settings in DDR2 Controller ...

Page 79: ...DE3 User Manual 76 Figure 5 19 Parameter Settings in DDR2 Controller ...

Page 80: ...Controller 3 Execute DDR2 TCL Files When DDR2 controller is created the IP will generate some TLC files Users must execute these TCL file first before start compiling otherwise Quartus will report error while compile To execute DDR2 TCL file click Tools Tcl Script to popup TCL scripts dialog as shown in Figure 5 21 Then execute the three marked TCl files individually ...

Page 81: ...Setup Make sure Quartus II and NIOS II are installed on your PC Make sure DDR2 SDRAM SODIMM is installed on your DE3 board as shown in Figure 5 13 Power on the DE3 board Connect USB Blaster to the DE3 board and install USB Blaster driver if necessary Execute the demo batch file de3_ddr2 bat under the batch file folder DE3_DDR2 demo_batch After NIOS II program is downloaded and executed successfull...

Page 82: ...DE3 User Manual 79 Figure 5 22 Insert DDR2 SDRAM SODIMM for the DDR2 Demonstration Figure 5 23 Display Progress and Result Information for the DDR2 Demonstration ...

Page 83: ...N 1 K2 3 3V High Logic Level when it is not pressed BUTTON2 BUTTON 2 M4 3 3V High Logic Level when it is not pressed BUTTON3 BUTTON 3 M3 3 3V High Logic Level when it is not pressed CPU RESET CPU_RST_N U31 3 3V User reset push button RECONFIGURE nCONFIG AE25 3 3V System re configuration push button Slide Switches Table A 2 Slide Switches pinout with FPGA Board Reference Signal Name FPGA Pin No I O...

Page 84: ...V High Logic Level when SW is in down position RGB LEDs Table A 4 RGB LEDs pinout with FPGA Board Reference Signal Name FPGA Pin No I O Standard Description LED0 LEDR 0 AD1 3 3V Red color of LED0 LED1 LEDR 1 AC1 3 3V Red color of LED1 LED2 LEDR 2 AC2 3 3V Red color of LED2 LED3 LEDR 3 AB2 3 3V Red color of LED3 LED4 LEDR 4 AC4 3 3V Red color of LED4 LED5 LEDR 5 AB4 3 3V Red color of LED5 LED6 LEDR...

Page 85: ...0 HEX0_D0 W12 3 3V Seven Segment Digit 0 0 HEX0 HEX0_D1 Y11 3 3V Seven Segment Digit 0 1 HEX0 HEX0_D2 W10 3 3V Seven Segment Digit 0 2 HEX0 HEX0_D3 W8 3 3V Seven Segment Digit 0 3 HEX0 HEX0_D4 W7 3 3V Seven Segment Digit 0 4 HEX0 HEX0_D5 Y5 3 3V Seven Segment Digit 0 5 HEX0 HEX0_D6 Y6 3 3V Seven Segment Digit 0 6 HEX1 HEX1_DP V4 3 3V Seven Segment Decimal Point 1 HEX1 HEX1_D0 P3 3 3V Seven Segment...

Page 86: ...10 N10 K30 Configurable HSTC connector IO TX_n 4 35 TX_p4 AD28 AC11 N11 K29 Configurable HSTC connector IO TX_p 4 39 TX_n5 AE30 AD6 K5 L29 Configurable HSTC connector IO TX_n 5 41 TX_p5 AE29 AD7 K6 L28 Configurable HSTC connector IO TX_p 5 45 TX_n6 AB27 AC7 N8 M28 Configurable HSTC connector IO TX_n 6 47 TX_p6 AB26 AB8 N9 N27 Configurable HSTC connector IO TX_p 6 51 TX_n7 AB25 AB9 L6 N26 Configura...

Page 87: ...ble A 8 The odd pins of bank2 on HSTC connectors pinout with FPGA Board Reference Signal Name FPGA Pin No I O Standard Description HSTC A HSTC B HSTC C HSTC D 63 CLKOUT_n1 AE18 AF16 K17 J19 Configurable HSTC connector CLKOUT n1 65 CLKOUT_p1 AD18 AE16 L17 K19 Configurable HSTC connector CLKOUT p1 69 TX_n9 AM21 AK15 A15 H20 Configurable HSTC connector IO TX_n 9 71 TX_p9 AP20 AG15 C14 E20 Configurabl...

Page 88: ...2 AH14 B13 G21 Configurable HSTC connector IO RX_p 10 82 RX_n11 AL21 AP12 E14 A23 Configurable HSTC connector IO RX_n 11 84 RX_p11 AK21 AN12 F14 B23 Configurable HSTC connector IO RX_p 11 88 RX_n12 AP24 AP10 A11 A25 Configurable HSTC connector IO RX_n 12 90 RX_p12 AN24 AN10 B11 B25 Configurable HSTC connector IO RX_p 12 94 RX_n13 AP25 AN9 A10 B26 Configurable HSTC connector IO RX_n 13 96 RX_p13 AN...

Page 89: ...figurable HSTC connector IO TX_n 20 143 TX_p20 AL28 AL7 E8 F26 Configurable HSTC connector IO TX_p 20 145 TX_n21 AP32 AP5 A5 A33 Configurable HSTC connector IO TX_n 21 147 TX_p21 AP30 AP2 A3 A30 Configurable HSTC connector IO TX_p 21 149 TX_n22 AH25 AN6 J12 B29 Configurable HSTC connector IO TX_n 22 151 TX_p22 AF23 AM6 G10 C29 Configurable HSTC connector IO TX_p 22 153 TX_n23 AH26 AM4 J11 D31 Conf...

Page 90: ...rable HSTC connector IO RX_n 21 148 RX_p21 AN31 AN4 B4 B31 Configurable HSTC connector IO RX_p 21 150 RX_n22 AP33 AP3 A2 A32 Configurable HSTC connector IO RX_n 22 152 RX_p22 AN33 AN3 B2 B32 Configurable HSTC connector IO RX_p 22 154 RX_n23 AH24 AM5 G11 C30 Configurable HSTC connector IO RX_n 23 156 RX_p23 AG24 AL5 H11 D30 Configurable HSTC connector IO RX_p 23 158 RX_n24 AN30 AK7 B5 E28 Configura...

Page 91: ... Configurable GPIO Expansion 0 IO 8 J10 14 GPIO0_D9 AJ31 Configurable GPIO Expansion 0 IO 9 J10 15 GPIO0_D10 AH34 Configurable GPIO Expansion 0 IO 10 J10 16 GPIO0_D11 AG32 Configurable GPIO Expansion 0 IO 11 J10 17 GPIO0_D12 AJ34 Configurable GPIO Expansion 0 IO 12 J10 18 GPIO0_D13 AG31 Configurable GPIO Expansion 0 IO 13 J10 20 GPIO0_D14 AF32 Configurable GPIO Expansion 0 IO 14 J10 22 GPIO0_D15 A...

Page 92: ... 1 IO 3 J11 7 GPIO1_D4 AE27 Configurable GPIO Expansion 1 IO 4 J11 8 GPIO1_D5 AD26 Configurable GPIO Expansion 1 IO 5 J11 9 GPIO1_D6 AD29 Configurable GPIO Expansion 1 IO 6 J11 10 GPIO1_D7 AF29 Configurable GPIO Expansion 1 IO 7 J11 13 GPIO1_D8 AD28 Configurable GPIO Expansion 1 IO 8 J11 14 GPIO1_D9 AF28 Configurable GPIO Expansion 1 IO 9 J11 15 GPIO1_D10 AB27 Configurable GPIO Expansion 1 IO 10 J...

Page 93: ...ie Termination 1 J9 30 DDR2_CLK_p0 AE4 SSTL 18 Class I Clock p0 for DDR2 J9 32 DDR2_CLK_n0 AE3 SSTL 18 Class I Clock n0 for DDR2 J9 164 DDR2_CLK_p1 AE11 SSTL 18 Class I Clock p1 for DDR2 J9 166 DDR2_CLK_n1 AF11 SSTL 18 Class I Clock n1 for DDR2 J9 79 DDR2_CKE0 AF6 SSTL 18 Class I Clock Enable pin 0 for DDR2 J9 80 DDR2_CKE1 AC11 SSTL 18 Class I Clock Enable pin 1 for DDR2 J9 5 DDR2_DQ0 AM1 SSTL 18 ...

Page 94: ...18 Class I DDR2 Data 29 J9 74 DDR2_DQ30 AP13 SSTL 18 Class I DDR2 Data 30 J9 76 DDR2_DQ31 AM12 SSTL 18 Class I DDR2 Data 31 J9 123 DDR2_DQ32 AP10 SSTL 18 Class I DDR2 Data 32 J9 125 DDR2_DQ33 AN10 SSTL 18 Class I DDR2 Data 33 J9 135 DDR2_DQ34 AF14 SSTL 18 Class I DDR2 Data 34 J9 137 DDR2_DQ35 AF13 SSTL 18 Class I DDR2 Data 35 J9 124 DDR2_DQ36 AP11 SSTL 18 Class I DDR2 Data 36 J9 126 DDR2_DQ37 AP9 ...

Page 95: ...ss I DDR2 Bank Address 2 J9 102 DDR2_A0 AE10 SSTL 18 Class I DDR2 Address 0 J9 101 DDR2_A1 AD12 SSTL 18 Class I DDR2 Address 1 J9 100 DDR2_A2 AF10 SSTL 18 Class I DDR2 Address 2 J9 99 DDR2_A3 AL14 SSTL 18 Class I DDR2 Address 3 J9 98 DDR2_A4 AJ6 SSTL 18 Class I DDR2 Address 4 J9 97 DDR2_A5 AM14 SSTL 18 Class I DDR2 Address 5 J9 94 DDR2_A6 AK6 SSTL 18 Class I DDR2 Address 6 J9 92 DDR2_A7 AM6 SSTL 1...

Page 96: ...p 7 J9 10 DDR2_DM0 AF5 SSTL 18 Class I DDR2 Data Mask 0 J9 26 DDR2_DM1 AB10 SSTL 18 Class I DDR2 Data Mask 1 J9 52 DDR2_DM2 AB9 SSTL 18 Class I DDR2 Data Mask 2 J9 67 DDR2_DM3 AN13 SSTL 18 Class I DDR2 Data Mask 3 J9 130 DDR2_DM4 AF15 SSTL 18 Class I DDR2 Data Mask 4 J9 147 DDR2_DM5 AP8 SSTL 18 Class I DDR2 Data Mask 5 J9 170 DDR2_DM6 AL8 SSTL 18 Class I DDR2 Data Mask 6 J9 185 DDR2_DM7 AN6 SSTL 1...

Page 97: ...1 P32 3 3V OTG Address 11 U2 B15 OTG_A12 R34 3 3V OTG Address 12 U2 A15 OTG_A13 R33 3 3V OTG Address 13 U2 B14 OTG_A14 R32 3 3V OTG Address 14 U2 A14 OTG_A15 T32 3 3V OTG Address 15 U2 A13 OTG_A16 U32 3 3V OTG Address 16 U2 C12 OTG_A17 R31 3 3V OTG Address 17 U2 R3 OTG_D0 Y25 3 3V OTG Data 0 U2 T3 OTG_D1 AA27 3 3V OTG Data 1 U2 R4 OTG_D2 Y26 3 3V OTG Data 2 U2 P5 OTG_D3 AA30 3 3V OTG Data 3 U2 T5 ...

Page 98: ... OTG Data 30 U2 K14 OTG_D31 AA29 3 3V OTG Data 31 U2 A12 OTG_CS_n P28 3 3V OTG Chip Select U2 B11 OTG_WE_n N29 3 3V OTG Write Enable U2 B12 OTG_OE_n N30 3 3V OTG Output Enable U2 B10 OTG_HC_IRQ P29 3 3V OTG Host Controller IRQ U2 A10 OTG_DC_IRQ R27 3 3V OTG Peripheral Controller IRQ U2 B6 OTG_RESET_n T23 3 3V OTG Reset U2 B9 OTG_HC_DREQ R28 3 3V OTG DMA Controller request for Host Controller U2 A8...

Page 99: ...ock for SD J12 11 SD_WPn N5 3 3V Write Protection for SD J12 7 SD_DAT0 P7 3 3V Data bit 0 for SD J12 2 SD_CMD R10 3 3V Command for SD Clock Table A 17 The clock pinout with FPGA Board Reference Signal Name FPGA Pin No I O Standard Description U19 3 OSC_BA AN18 Configurable Clock input for I O Group A U19 5 OSC_BB AN16 Configurable Clock input for I O Group B U19 7 OSC_BC B17 Configurable Clock inp...

Page 100: ...No I O Standard Description U5 3 TEMPDIODEn D4 3 3V Negative pin of Temperature Diode in Stratix III U5 4 TEMPDIODEp E5 3 3V Positive pin of Temperature Diode in Stratix III U5 9 TEMP_OVERn Overtemperature Alarm U5 11 TEMP_INTn N2 3 3V SMBus Alert interrupt U5 12 TEMP_DATA P1 3 3V SMBus Data U5 14 TEMP_CLK P4 3 3V SMBus Clock ...

Page 101: ...10 RX_n0 152 LVDS_RXn16 LVDS D75 CMOS 11 TX_p0 149 LVDS_TXp16 LVDS D72 CMOS 12 RX_p0 150 LVDS_RXp16 LVDS D73 CMOS 15 TX_n1 145 LVDS_TXn15 LVDS D70 CMOS 16 RX_n1 146 LVDS_RXn15 LVDS D71 CMOS 17 TX_p1 143 LVDS_TXp15 LVDS D68 CMOS 18 RX_p1 144 LVDS_RXp15 LVDS D69 CMOS 21 TX_n2 139 LVDS_TXn14 LVDS D66 CMOS 22 RX_n2 140 LVDS_RXn14 LVDS D67 CMOS 23 TX_p2 137 LVDS_TXp14 LVDS D64 CMOS 24 RX_p2 138 LVDS_RX...

Page 102: ...p CMOS D36 LVDS_CLKp CMOS 66 CLKIN_p1 96 CLKIN1p LVDS_CLKp CMOS D37 LVDS_CLKp CMOS 69 TX_n9 91 LVDS_TXn7 LVDS D34 CMOS 70 RX_n9 92 LVDS_RXn7 LVDS D35 CMOS 71 TX_p9 89 LVDS_TXp7 LVDS D32 CMOS 72 RX_p9 90 LVDS_RXp7 LVDS D33 CMOS 75 TX_n10 85 LVDS_TXn6 LVDS D30 CMOS 76 RX_n10 86 LVDS_RXn6 LVDS D31 CMOS 77 TX_p10 83 LVDS_TXp6 LVDS D28 CMOS 78 RX_p10 84 LVDS_RXp6 LVDS D29 CMOS 81 TX_n11 79 LVDS_TXn5 LV...

Page 103: ...TAG_TDO JTAG CMOS JTAG_TDO JTAG CMOS 126 TDI 38 JTAG_TDI JTAG CMOS JTAG_TDI JTAG CMOS 129 TCK 35 JTAG_TCK JTAG CMOS JTAG_TCK JTAG CMOS 130 TMS 36 JTAG_TMS JTAG CMOS JTAG_TMS JTAG CMOS 131 SDA 33 SDA SMBUS CMOS SDA SMBUS CMOS 132 SCL 34 SCL SMBUS CMOS SCL SMBUS CMOS 133 TX_n18 134 RX_n18 135 TX_p18 31 TXVR_TXn0 Transceiver D110 CMOS 136 RX_p18 32 TXVR_RXn0 Transceiver D111 CMOS 137 TX_n19 29 TXVR_T...

Page 104: ...n25 14 TXVR_RXp4 Transceiver D91 CMOS 163 TX_p25 164 RX_p25 165 TX_n26 11 TXVR_TXn5 Transceiver D90 CMOS 166 RX_n26 12 TXVR_RXn5 Transceiver D91 CMOS 167 TX_p26 9 TXVR_TXp5 Transceiver D88 CMOS 168 RX_p26 10 TXVR_RXp5 Transceiver D89 CMOS 169 TX_n27 170 RX_n27 171 TX_p27 7 TXVR_TXn6 Transceiver D86 CMOS 172 RX_p27 8 TXVR_RXn6 Transceiver D87 CMOS 173 TX_n28 5 TXVR_TXp6 Transceiver D84 CMOS 174 RX_...

Page 105: ... a JIC file in Quartus II software follow these steps Convert SOF to JIC 1 Choose Convert Programming Files File menu 2 In the Convert Programming Files dialog box scroll to the JTAG Indirect Configuration File jic from the Programming file type field 3 In the Configuration device field specify the targeted serial configuration device For DE3 340 and DE3 260 please select EPCS128 For DE3 150 pleas...

Page 106: ...DE3 User Manual 103 Figure C 1 Convert Programming Files Dialog Box Figure C 2 Highlight Flash Loader ...

Page 107: ...1 Select the targeted FPGA that you are using to program the serial configuration device See Figure C 3 12 Click OK The Convert Programming Files page displays See Figure C 4 13 Click Generate Figure C 3 Select Devices Page ...

Page 108: ...window and follow the steps 1 When the SOF to JIC file conversion is complete add the JIC file to the Quartus II Programmer window i Choose Programmer Tools menu The Chain1 cdf window displays ii Click Add File From the Select Programming File page browse to the JIC file iii Click Open 2 Program the serial configuration device by checking the corresponding Program Configure box a Factory default S...

Page 109: ...erase the existed file in the serial configuration device follow the steps listed below 1 Choose Programmer Tools menu The Chain1 cdf window displays 2 Click Add File From the Select Programming File page browse to a JIC file 3 Click Open 4 Erase the serial configuration device by checking the corresponding Erase box a Factory default SFL image will be load See Figure C 6 ...

Page 110: ...DE3 User Manual 107 Figure C 6 Erasing setting in Quartus II programmer window 5 Click Start to erase the serial configuration device ...

Page 111: ...card to the HSTC connector which is needed to be tested as shown in Figure D 2 5 Turn on the power of the DE3 board and connect the USB cable to the USB Blaster port on the DE3 board 6 In the DE3_HSTC utility window press Test HSTC A button to start testing the HSTC connector A as shown in Figure D 3 7 The test result will be reported on the panel of the DE3_HSTC utility as shown in Figure D 4 8 I...

Page 112: ...DE3 User Manual 109 Figure D 1 The THDB_HLB adapter card Figure D 2 The connection setup for THDB HLB and DE3 board ...

Page 113: ...DE3 User Manual 110 Figure D 3 The DE3_HSTC utility Figure D 4 The test result of the HSTC connector A ...

Page 114: ...DE3 User Manual 111 Figure D 5 The reported message of the invalid I O pins ...

Page 115: ... termination resistor on the differential transmitter channel Table E 1 The distribution of the differential termination resistors for HSTC connector Differential Pair Signal Name Part name of the differential termination resistor HSTC A HSTC B HSTC C HSTC D 9 TX_p9 TX_n9 R3 R27 R51 R75 10 TX_p10 TX_n10 R4 R28 R52 R76 11 TX_p11 TX_n11 R5 R29 R53 R77 12 TX_p12 TX_n12 R6 R30 R54 R78 13 TX_p13 TX_n13...

Page 116: ...on resistor HSTC A HSTC B HSTC C HSTC D 23 TX_p23 TX_n23 R17 R41 R65 R89 24 TX_p24 TX_n24 R18 R42 R66 R90 25 TX_p25 TX_n25 R19 R43 R67 R91 26 TX_p26 TX_n26 R20 R44 R68 R92 27 TX_p27 TX_n27 R21 R45 R69 R93 28 TX_p28 TX_n28 R22 R46 R70 R94 29 TX_p29 TX_n29 R23 R47 R71 R95 CLK1_IN HSTCA_CLKIN_n1 HSTCA_CLKIN_p1 R1 R25 R49 R73 CLK1_OUT HSTCA_CLKOUT_n1 HSTCA_CLKOUT_p1 R2 R26 R50 R74 ...

Page 117: ...ER ON pin on HSTC connector Add section 5 4 DDR2 demonstration Modify section 2 2 Add Figure 2 14 and Figure 2 15 Modify Table A 12 Table A 12 2008 12 25 V1 2 1 Modify Figure 2 14 2009 1 5 V 1 2 2 Modify Figure 2 12 2009 1 9 V 1 2 3 Modify Figure 1 2 and Figure 1 4 Modify section 1 2 and Appendix C 2009 2 1 V 1 2 4 Modify Figure 1 2 and Figure 1 4 Modify Table A 13 2009 3 5 V 1 2 5 Modify file pat...

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