Terasic Altera DE3, User Manual

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DE3 User Manual
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J11-32 GPIO1_D23 AJ21 Configurable GPIO Expansion 1 IO[23]
J11-33 GPIO1_D24 AD21 Configurable GPIO Expansion 1 IO[24]
J11-34 GPIO1_D25 AP26 Configurable GPIO Expansion 1 IO[25]
J11-35 GPIO1_D26 AE20 Configurable GPIO Expansion 1 IO[26]
J11-36 GPIO1_D27 AP23 Configurable GPIO Expansion 1 IO[27]
J11-37 GPIO1_D28 AK24 Configurable GPIO Expansion 1 IO[28]
J11-38 GPIO1_D29 AE22 Configurable GPIO Expansion 1 IO[29]
J11-39 GPIO1_D30 AL25 Configurable GPIO Expansion 1 IO[30]
J11-40 GPIO1_D31 AE21 Configurable GPIO Expansion 1 IO[31]
DDR2 SO-DIMM Socket
Table A-14 DDR2 SO-DIMM socket pinout with FPGA
Board
Reference
Signal Name
FPGA
Pin No.
I/O
Standard
Description
J9-114 DDR2_ODT0 AM15 SSTL-18 Class I DDR2 On Die Termination[0]
J9-119 DDR2_ODT1 AJ16 SSTL-18 Class I DDR2 On Die Termination[1]
J9-30 DDR2_CLK_p0 AE4 SSTL-18 Class I Clock p0 for DDR2
J9-32 DDR2_CLK_n0 AE3 SSTL-18 Class I Clock n0 for DDR2
J9-164 DDR2_CLK_p1 AE11 SSTL-18 Class I Clock p1 for DDR2
J9-166 DDR2_CLK_n1 AF11 SSTL-18 Class I Clock n1 for DDR2
J9-79 DDR2_CKE0 AF6 SSTL-18 Class I Clock Enable pin 0 for DDR2
J9-80 DDR2_CKE1 AC11 SSTL-18 Class I Clock Enable pin 1 for DDR2
J9-5 DDR2_DQ0 AM1 SSTL-18 Class I DDR2 Data [0]
J9-7 DDR2_DQ1 AM2 SSTL-18 Class I DDR2 Data [1]
J9-17 DDR2_DQ2 AL
1
SSTL-18 Class I DDR2 Data [2]
J9-19 DDR2_DQ3 A
L2
SSTL-18 Class I DDR2 Data [3]
J9-4 DDR2_DQ4 AE
7
SSTL-18 Class I DDR2 Data [4]
J9-6 DDR2_DQ5 AE8 SSTL-18 Class I DDR2 Data [5]
J9-14 DDR2_DQ6 AC8 SSTL-18 Class I DDR2 Data [6]
J9-16 DDR2_DQ7 AC9 SSTL-18 Class I DDR2 Data [7]
J9-23 DDR2_DQ8 AG3 SSTL-18 Class I DDR2 Data [8]
J9-25 DDR2_DQ9 AG4 SSTL-18 Class I DDR2 Data [9]
J9-35 DDR2_DQ10 AJ1 SSTL-18 Class I DDR2 Data [10]
J9-37 DDR2_DQ11 AH2 SSTL-18 Class I DDR2 Data [11]
J9-20 DDR2_DQ12 AE5 SSTL-18 Class I DDR2 Data [12]