Terasic Altera DE3, User Manual

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DE3 User Manual
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blue color, driven directly by the Stratix III FPGA; The LED is turned on or off when the
associated pins are driven to a low or high logic level, respectively. A list of the pin names on
the FPGA that are connected to the RGB LEDs is given in Table A-4.
7-Segment Displays
The DE3 board has two 7-segment displays. As indicated in the schematic in Figure 2.8 , the
seven segments are connected to pins of the Stratix III FPGA. Applying a low or high logic
level to a segment to light it up or turns it off.
Each segment in a display is identified by an index listed from 0 to 6 with the positions given
in Figure 2.9. In addition, the decimal point is identified as DP. Table A-5 shows the mapping
of the FPGA pin assignments to the 7-segment displays.
3
7
9
8
5
10
4
2
HEX1_D0
M1
L1
L2
V4
P3
N4
Y11
W12
Y5
Y6
V3
HEX1
HEX0
HEX1_D1
HEX1_D2
HEX1_D3
HEX1_D4
HEX1_D5
HEX1_D6
HEX1_DP
HEX0_D0
HEX0_D1
HEX0_D2
HEX0_D3
HEX0_D4
HEX0_D5
HEX0_D6
HEX6_DP
N3
N1
W7
W8
W10
3
7
9
8
5
10
4
2
Figure 2.8. Connection between 7-segment displays and Stratix III FPGA
0
3
1
2 4
5
6
DP
Figure 2.9. Position and index of each segment in a 7-segment display
2.4 I/O Groups and V
CCIO
Control Circuit
Most of the user-defined I/O pins on Stratix III device are used for connectors. They are divided