DE3 User Manual
42
The top-level deign file contains top-level verilog wrapper for users to add their own design/logic.
The encrypted power configuration controller file contains encrypted core which is generated by
user’s selection on I/O Group voltage. The Quartus II setting file contains information such as
FPGA device type, top-level pin assignment, and I/O standard for each user-defined I/O pin.
Next, users must be aware that they can never modify encrypted power configuration controller file.
User’s own design should be included within top-level deign file.
Finally, Quartus II programmer must be used to download SOF file to DE3 board using JTAG
interface.
Start
Launch
DE3 System Builder
Create New
DE3 System Builder
Project
.QPF
.QSF
.V
.HTML
.SDC
Generate
Quartuss II Project
and Document
Launch Quartus II and
Open Project
Add User Design/
Logic
Compile to generate
.SOF
Configure FPGA
End
Figure 4.1. The general design flow of building a design
for the DE3 board via the DE3 System Builder
Summary of Contents for Altera DE3
Page 1: ...Altera DE3 Board ...
Page 67: ...DE3 User Manual 64 Figure 5 5 Plug USB Devices into DE3 Figure 5 6 Display Device Information ...
Page 75: ...DE3 User Manual 72 Figure 5 14 Display SD Card Information for the SD Card Demonstration ...
Page 79: ...DE3 User Manual 76 Figure 5 19 Parameter Settings in DDR2 Controller ...
Page 114: ...DE3 User Manual 111 Figure D 5 The reported message of the invalid I O pins ...
