Terasic Altera DE3, User Manual

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DE3 User Manual
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into four I/O groups, named A, B, C and D. Table 2-2 shows the relation between I/O groups and
connectors.
Table 2-2 The relation between I/O groups and connectors
I/O Group Connectors
A HSTC connector A, GPIO expansion headers (1)
B HSTC connector B, DDR2 SO-DIMM socket (2)
C HSTC connector C
D HSTC connector D
Note:
(1) : HSTC connector A and GPIO expansion headers share the same I/O pins.
(2) : HSTC connector B and DDR2 SO-DIMM socket share the same I/O pins.
Besides, the V
CCIO
level for these I/O groups of the FPGA can be configured, and many I/O
standards are supported. The I/O standard of each I/O group on DE3 board has to be set through a
software utility named “DE3 System Builder”. Such tool is intended to generate a top level
Quartus II project, which includes the power controller IP.
After the FPGA is programmed, the power controller IP will control the V
CCIO
control circuit to
provide desired V
CCIO
and V
CCPD
level to the FPGA, according to I/O standard selected by users as
indicated in Figure 2.10 . With this feature, users can not only confirm if the V
CCIO
level meets the
design requirement, but also reduce the chance of the DE3 board and its daughter cards being
damaged.
Please refer to Stratix III handbook chapter 7. Stratix III Device I/O Features for more information
about the I/O standard and voltage levels of the Stratix III device. There will be more instructions
for DE3 System Builder in Chapter 4.
V
CCIO
Selection
Power Control
IP
V
CCIO
to I/O bank
V
CCIO
Voltage-Level
Control Circuit
Figure 2.10. The architecture of Power Control IP and V
CCIO
control circuit