DE3 User Manual
56
6.
Complete the project:
Click Generate to complete this project, and the DE3 System Builder will generate two
Quartus II projects named DE3_TOP and DE3_BOTTOM.
7.
Add custom design:
i.
The DE3_System_Builder will generate the HSTC connector port name and
set the I/O direction to bi-directional in the top-level file:
////////// HSTCA (J1, HSTC-A TOP/J2, HSTC-A BOTTOM), connect to DE3
//////////
inout [129:0] HSTCA_IO;
inout
HSTCA_SDA;
output
HSTCA_SCL;
////////// HSTCB (J3, HSTC-B TOP/J4, HSTC-B BOTTOM), connect to DE3
//////////
inout [129:0] HSTCB_IO;
inout
HSTCB_SDA;
output
HSTCB_SCL;
.
.
.
ii.
User can include user logic design to the top-level file and compile the project
to generate the SOF file.
8.
Configure the FPGA device
4.7
Connect a Custom-Made Daughter Board to the DE3 Board
If users want to connect a custom-made daughter board to the DE3 board, the most important thing
is to make sure that both DE3 board and the custom daughter board support the same I/O standard.
The following example shows how to connect a custom daughter board with 3.3V I/O standard to
the GPIO connector of the DE3 board.
1.
Executable DE3_System_Builder.exe on the host computer.
2.
Add a DE3 board.
3.
Configure the DE3 I/O interface:
Please refer to the
Figure 4.19
to modify the associated configuration as described
below:
i.
Change the Board Name from DE3 to DE3_CUSTOM_DESIGN.
ii.
Make sure the FPGA type is the same as user’s DE3 board.
Summary of Contents for Altera DE3
Page 1: ...Altera DE3 Board ...
Page 67: ...DE3 User Manual 64 Figure 5 5 Plug USB Devices into DE3 Figure 5 6 Display Device Information ...
Page 75: ...DE3 User Manual 72 Figure 5 14 Display SD Card Information for the SD Card Demonstration ...
Page 79: ...DE3 User Manual 76 Figure 5 19 Parameter Settings in DDR2 Controller ...
Page 114: ...DE3 User Manual 111 Figure D 5 The reported message of the invalid I O pins ...