Terasic Altera DE3, User Manual

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DE3 User Manual
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Appendix A
Pin connections between components
and FPGA on the DE3 board
A
Appendix A: Pin connections between components and FPGA on the DE3 board
This appendix lists the connections between components and Stratix III FPGA on the DE3 board.
Push-Button Switches
Table A-1. Push-button switches pinout with FPGA
Board
Reference
Signal Name
FPGA
Pin No.
I/O
Standard
Description
BUTTON0 BUTTON[0] K1 3.3V High Logic Level when it is not pressed
BUTTON1 BUTTON[1] K2 3.3V High Logic Level when it is not pressed
BUTTON2 BUTTON[2] M4 3.3V High Logic Level when it is not pressed
BUTTON3 BUTTON[3] M3 3.3V High Logic Level when it is not pressed
CPU RESET CPU_RST_N U31 3.3V User reset push-button
RECONFIGURE nCONFIG AE25 3.3V System re-configuration push-button
Slide Switches
Table A-2 Slide Switches pinout with FPGA
Board
Reference
Signal Name
FPGA
Pin No.
I/O
Standard
Description
SW0 SW0 W5 3.3V High Logic Level when SW is in upper position
SW1 SW1 W6 3.3V High Logic Level when SW is in upper position
SW2 SW2 W9 3.3V High Logic Level when SW is in upper position
SW3 SW3 W11 3.3V High Logic Level when SW is in upper position