Terasic Altera DE3, User Manual

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DE3 User Manual
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5.4 DDR2 SDRAM
Many applications use a high performance RAM, such as a DDR2 SDRAM, as temporary storage.
The DE3 board provides the hardware and software designs for accessing DDR2 SDRAM
SODIMM. In this demonstration, we show how to use Altera’s “DDR2 SDRAM High Performance
Controller” IP to build DDR2-SDRAM controller, and how to use NIOS processor to read and write
the SDRAM for hardware verification. The required DDR2-SDRAM SODIMM module should be
256M-Bytes DDR2-533 at least. In the demonstration, we only provide 256M-Bytes accessing for
SDRAM due to SOPC builder limitation. For none SOPC project, users can change the DDR2 IP
setting to support higher capacity of SDRAM.
Figure 5.15 shows the system block diagram of this demonstration. The system requires a 50 MHz
clock provided from the board. The DDR2 controller is configured as a 256M-Bytes DDR2-533
controller. The DDR2 IP generates one 266.667 MHZ clock as SDRAM’s data clock and one
half-rate system clock 133.333 MHZ for those controllers, e.g. NIOS processor, accessing the
SDRAM. In the SOPC, NIOS and On-Chip Memory are designed running with the 133.333 MHZ
clock, and the other controllers are designed running with 20 MHZ clock which is generated by the
PLL. The NIOS program is running in the 128K-Bytes on-chip memory.
Figure 5.15. Block Diagram of the DDR2 Demonstration