Terasic Altera DE3, User Manual

Page: 91 / 117

DE3 User Manual
88
GPIO Expansion Header
Table A-12 GPIO Expansion Header 0 pinout with FPGA
Board
Reference
Signal Name
FPGA
Pin No.
I/O
Standard
Description
J10-1 GPIO0_CLKINn0 AE32 Configurable GPIO Expansion 0 Clock In
J10-3 GPIO0_CLKINp0 AE31 Configurable GPIO Expansion 0 Clock In
J10-19 GPIO0_CLKOUTn0 AE19 Configurable GPIO Expansion 0 PLL Out
J10-21 GPIO_CLKOUTp0 AD19 Configurable GPIO Expansion 0 PLL Out
J10-2 GPIO0_D0 AL33 Configurable GPIO Expansion 0 IO[0]
J10-4 GPIO0_D1 AL32 Configurable GPIO Expansion 0 IO[1]
J10-5 GPIO0_D2 AL34 Configurable GPIO Expansion 0 IO[2]
J10-6 GPIO0_D3 AH31 Configurable GPIO Expansion 0 IO[3]
J10-7 GPIO0_D4 AM34 Configurable GPIO Expansion 0 IO[4]
J10-8 GPIO0_D5 AH30 Configurable GPIO Expansion 0 IO[5]
J10-9 GPIO0_D6 AK34 Configurable GPIO Expansion 0 IO[6]
J10-10 GPIO0_D7 AJ32 Configurable GPIO Expansion 0 IO[7]
J10-13 GPIO0_D8 AK33 Configurable GPIO Expansion 0 IO[8]
J10-14 GPIO0_D9 AJ31 Configurable GPIO Expansion 0 IO[9]
J10-15 GPIO0_D10 AH34 Configurable GPIO Expansion 0 IO[10]
J10-16 GPIO0_D11 AG32 Configurable GPIO Expansion 0 IO[11]
J10-17 GPIO0_D12 AJ34 Configurable GPIO Expansion 0 IO[12]
J10-18 GPIO0_D13 AG31 Configurable GPIO Expansion 0 IO[13]
J10-20 GPIO0_D14 AF32 Configurable GPIO Expansion 0 IO[14]
J10-22 GPIO0_D15 AF31 Configurable GPIO Expansion 0 IO[15]
J10-23 GPIO0_D16 AP21 Configurable GPIO Expansion 0 IO[16]
J10-24 GPIO0_D17 AG34 Configurable GPIO Expansion 0 IO[17]
J10-25 GPIO0_D18 AN21 Configurable GPIO Expansion 0 IO[18]
J10-26 GPIO0_D19 AH33 Configurable GPIO Expansion 0 IO[19]
J10-27 GPIO0_D20 AL21 Configurable GPIO Expansion 0 IO[20]
J10-28 GPIO0_D21 AP22 Configurable GPIO Expansion 0 IO[21]
J10-31 GPIO0_D22 AK21 Configurable GPIO Expansion 0 IO[22]
J10-32 GPIO0_D23 AN22 Configurable GPIO Expansion 0 IO[23]
J10-33 GPIO0_D24 AP25 Configurable GPIO Expansion 0 IO[24]
J10-34 GPIO0_D25 AP24 Configurable GPIO Expansion 0 IO[25]
J10-35 GPIO0_D26 AN25 Configurable GPIO Expansion 0 IO[26]