Telecommunications Techniques Corporation interceptor 147, Reference Manual, Page: 248 / 280

Remote Control Status Registers
C-4
C
INTERCEPTOR 147 2 Mbit/s and Data Analyzer
STATUS BYTE REGISTER
(*STB?)
SERVICE REQUEST ENABLE REGISTER
0 0
0 0 0
EVENT SUMMARY
TEST SUMMARY BIT
PRINT AVAILABLE
ERROR AVAILABLE
0
MASTER STATUS
SUMMARY
0
0
Figure C-3
Status Byte Register
The controller reads the Status Byte Register by using a
serial poll or the *STB query. If the Status Byte Register
is read using a serial poll, bit 6 is returned as a Request
Service (RQS); if it is read with a *STB? query, bit 6 is
returned as a Master Summary Status (MSS).
When the Status Byte Register is read, a binary-weighted
integer is returned. This integer represents the decimal
equivalent of the enabled bits in the register. Convert the
returned value to binary to determine the status of the bits
in the Status Byte Register.
Bit 7 Not Defined. Always set to 0.
Bit 6 MSS - Master Status Summary
Represents the summary of all other bits in
the Status Byte Register. The corresponding
enabling bit in the Service Request Enabling
Register (*SRE) is not programmable.
Bit 5 ESB - Event Status Bit
Indicates that an enabled event in the Standard
Event Status Register has occurred. Read
the Standard Event Status Register to
determine which event has occurred.