Telecommunications Techniques Corporation interceptor 147, Reference Manual, Page: 195 / 280

7-15
7
INTERCEPTOR 147 2 Mbit/s and Data Analyzer
Applications
can also be used to perform in-service tests on 2048
kbit/s circuits from DS3 monitor points. For a diagram of
a typical test setup, see Figure 7-6.
Figure 7-6
Monitoring a 2 Mbit/s Circuit From a
DS3 Access Point
NOTE:
Use the instructions below to set up the receiving
INTERCEPTOR 147 located at the DS3 monitor
point. It is assumed that the transmitting 2048
kbit/s test set has been configured to generate a
suitable test pattern, such as 2^15-1 or 2^23-1
and has been configured to use the framing mode
normally used on the 2048 kbit/s circuit under
test. It is also assumed that the T-BERD 305 or
T-BERD 310 has been properly configured to
drop the 2048 kbit/s circuit under test.
Test Setup
1. Perform the Basic Setup Procedure
Verify the PANEL LOCK and SELF LOOP
LEDs are off.
2. Set Test to 2M and Test Mode to 2048K
DS3
SONET
or SDH
Mux
2.048 Mbit/s
Test Pattern
MON
DS3
Circuits
SONET/SDH
Network
SONET
or SDH
Mux
2.048
Mbit/s
Test
Pattern
2.048 Mbit/s
"End Link"
DS3
Mux
DS3
Circuits
INTERCEPTOR 147
TX
RX
DATA
INTERCEPTOR
264
T-BERD 305/310