Tektronix 80A00, Technical Reference

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Optical Sampling Modules
Table 12: Clock recovery settings (cont.)
Optical sampling module Clock recovery rate D3186 rate setting DSA8300 scale setting
80C11-CR1, 80C11B-CR1 OC-192 9.95328 Gb/s 50 ps/div
OC-192 9.95328 Gb/s 50 ps/div 80C11-CR2, 80C11B-CR1
10.66 FEC 10.66423 Gb/s 50 ps/div
OC-192 9.95328 Gb/s 50 ps/div 80C11-CR3, 80C11B-CR3
FEC10.71 10.709225 Gb/s 50 ps/div
80C11-CR4, 80C11B-CR4 Continuous 9.8 Gb/s to 12.6 Gb/s 50 ps/div
At this point in the procedure, the main instrument is triggered from the 1/32
clock from the D3186 Pulse Pattern Generator. The clock signal from the
80Cxx-CR Optical Sampling Module that is connected to C3 on the 80E02
Sampling Module should be synchronous with the signal from the pulse
pattern generator. (See Figure 36.)
If the signals are not synchronous as shown in the following fi gure), check
that the D3186 data rate is set to a data rate that matches the clock recovery
rate set for the 80C0X-CR Optical Sampling Module. (See Table 12.)
The following fi gure is an example of the display when the clock signal from
the Optical Sampling Module is not synchronous with the data rate input.
Note the unstable (“washed out”) clock signal. Compare this with the next
fi gure, in which the clock signal is synchronized.
Figure 35: Display example (clock signal not synchronized with the data rate input)
4. Once you have veri fi ed that the recovered clock signal (C3) is locked with the
incoming data, select the Mode/Trigger dialog box tab, Click Clock as the
Trigger Source, and select C3 Clock Recovery as the Trigger Source.
246 DSA8300 Performance Veri fi cation