Tektronix 2246 1Y, Service Manual

Page: 66 / 433

Theory of Operation—2246 1Y and 2246 Mod A Service
all. When DM1 and DM0 = 10, the B Sweep won’t be
allowed to run or trigger until the DLY12 input goes
high while the A GATE signal is also high (the normal
delayed sweep mode). When DM1 and DM0 = 01,
the B Sweep will be allowed to run or trigger immedi­
ately after the A GATE signal goes high (no B Sweep
delay). When DM1 and DM0 = 00, then the B Sweep
will be allowed to run or trigger immediately after the
A GATE signal goes high, if the DS (delay select)
input is high. If DS is low, the B Sweep is allowed to
run or trigger as soon as the DLY12 input goes high
while the A GATE signal is also high.
The B Sweep logic behaves as follows. The B GATE
signal goes high and BUB (B Sweep unblanking)
goes low together when the appropriate conditions
(described in the preceding paragraph) are met. A
low -to-high transition on the EOBS input will then set
the e nd-of-B -sw eep latch, causing BUB to go high.
B GATE doesn’t go low until the A GATE signal goes
low. This is used internally to generate the S2 and
S3 outputs in some modes, and is used externally to
carry out the B ends A mode.
The DLY12 input goes to a level-sensitive latch; if A
GATE is high and DLY12 momentarily goes high, the
latch will be set, so that the DLY12 input does not
need to be held high throughout the sweep cycle. A
high level on the THO input will cause the A GATE
signal to go low. That resets this latch and causes
the reset of the rest of the sweep logic, forcing B
GATE low and BUB high.
The DLY2 input also goes to a level sensitive latch.
This second latch also gets reset when A GATE goes
low. Together with the DLY1 latch output, A GATE,
and the MGE input, the C GATE output signal gets
generated (not used externally in the 2246 1Y and
2246 Mod A). C GATE goes low if A GATE is high,
the DLY1 latch has been set, the DLY2 latch is still
reset, and the MGE input is low.
Peak Volts Logic
The peak volts logic detects the positive and nega­
tive peaks of the B TRIG signal. It consists of a level-
sensitive latch that can be gated by the C GATE
signal, the A GATE signal, the DLY12 latch output, or
continuously. The latch may be reset by strobing the
SIN input with A1 and A0 set to 11. The latch output
can be read at the TDO pin with A1 and A0 set this
way. The Measurement Processor reads the state of
the peak volts latch to determine when it has found
the correct digital value of the signal peak being
measured by the B Trigger Level Comparator.
The peak-detect latch output will go high when the B
TRIG input goes high (if the gating condition selected
by PM1 and PM0 is satisfied). The latch output goes
low when reset.
Strobed Volts Logic
This logic samples the state of the B TRIG signal with
the delay comparator outputs when making gated
voltage measurements. The strobed volts latch con­
sists of an edge-triggered flip-flop with a multiplexer
driving the clock input, and the B TRIG signal driving
the D input. When MSEL=1, the DLY12 latch output
clocks the flip-flop. When MSEL=0, the DLY2 latch
output clocks the flip-flop. The state of the flip-flop
is read out at the TDO pin by the Measurement
Processor when A1, A0 = 00. The flip-flop is reset
by strobing the SIN input with A 1, A0 = 11.
Z-Axis Logic
This logic drives the Z-Axis control outputs
( ST - S4) • These outputs have the following control
action:
ST Turns on the A intensity current switch
(active low).
S2 Turns on the B intensity current switch
(active low).
53 Turns on the A intensified current switch
(active low).
54 Turns on the Readout intensity current switch
(active low).
Table 3-21 describes what the SI - S4 outputs do
as a function of ZM1, ZM0, HD1, HD0, AGATE,
BUB, C GATE, BUSY, BLANK, and ZEN.
3-29