Tektronix 2246 1Y, Service Manual

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T h e o ry of O p eratio n —2246 1Y and 2246 M od A Service
NOTES (c o n t):
(g) NSSS = The number of states programmed into the vertical sequencer.
(h) Programmable with the vertical sequencer.
(i) Programmable with the vertical sequencer. There are two A Sweeps per vertical display state.
Sweep Gate Detection
Display Logic 1C U600 also contains sweep gate
detect latches that can be read out and reset via the
Measurement Processor interface. The A GATE
detect latch output will go high on the rising edge of
A GATE after a falling edge of A GATE, if the MGE
signal is low (i.e., the latch is armed by MGE). The
B GATE detect latch output goes high when B GATE
goes low (level sensitive). The A GATE latch is reset
on the leading edge of the A/B RESET signal, so that
the latch will not miss an A GATE occurring before
the end of the latch reset interval. The B GATE latch
resets when the A/B RESET signal is low.
Chop Clock
The clock frequency applied to the TC input pin is
either divided by 8 (FSEL = 0), or divided by 16
(FSEL = 1 ) , producing a positive-going pulse at the
BLANK output pin (when enabled) with a width equal
to about two times the period of the clock signal on
the TC input. To produce phase skewing, the chop
frequency divider circuit is forced to skip ahead by
four TC clock periods on a rising edge of A GATE.
This skipping is gated on and off by applying a
low-frequency clock signal (about 1 kHz from the
Calibrator circuit) to the LFC (low-frequency clock)
input pin. Internally, the LFC signal is divided by two,
and when the resulting square wave is high, count
skip-ahead is enabled.
Readout Interface
The Readout Interface accepts inputs from the ROR
and ROB pins, and drives the BLANK output pin.
When ROR is high, the BLANK output is controlled by
the chop blank signal (when enabled by the CBEN
control bit).
When the ROR input is low, chop blanking is disabled
and the ROB input is inverted and allowed to control
the BLANK output. When the ROR input goes from
low to high, the BLANK output remains connected to
the readout blank signal for an additional four to six
TC clock periods. Normally, the ROB input will be low
during this time so that the BLANK output will be high
to mask vertical source-switching transients. The
HD1, HDO, and TS outputs are disabled two to four
TC periods after ROR goes low, and are again
enabled two TC periods before the BLANK output is
disconnected from the readout blank signal (ROB).
For any readout request cycle, the ROR input
remains low for greater than six TC clock periods.
Relative timing of ROR, BLANK, HDO and HD1 (HDx),
TS, and vertical channel enables (CH x EN) is shown
in Figure 3-2.
3-25
Figure 3-2. Readout interface relative signal timing.