Tektronix 2246 1Y, Service Manual

Page: 46 / 433

Theory of Operation—2246 1Y and 2246 Mod A Service
Table 3-3
CH 1 and CH 2 Attenuator and Gain Control Bit States
VOLTS/DIV
CH 1 X I 0 2
or
CH 2 X10 2
CH 1 XI
or
CH 2 XI
NC
CH 1 X5
or
CH 2 X5
CH 1 PREAMP 1
or
CH 2 PREAMP 1
CH 1 PREAMP 0
or
CH 2 PREAMP 0
CH 1 X10 1
or
CH 2 X10 1
2 mV 1 0 1 0 0 0 0
5 mV
1 0 1 0 0 0
1
10 mV
1
0
1 0 0 1 1
20 mV 1 0 0
1 0 1 1
50 mV 1 0 0 0 1 1
1
100 mV
1 1 1
0 0
1 1
200 mV 1 1 0 1 0 1 1
500 mV 1 1 0 0 1 1 1
1 V
0
1 1
0 0
1 1
2 V 0 1 0 1 0 1 1
5 V 0
1
0 0
1 1 1
VERTICAL PREAMPS AND OUTPUT
AMPLIFIER (Diagram 2)
Vertical Preamplifiers
Each input channel has it own Vertical Preamplifier
(CH 1-1)210, CH 2-U220, CH 3-U230, CH 4-U240).
The gain setting of the Preamplifier is controlled by
Measurement Processor U2501 via the assigned con­
trol bits from Shift Register 0 (see Table 3 -3 ). Chan­
nel 1 and Channel 2 gains require two control bits (on
pins 1 and 2 of the Preamplifiers) to set three different
gains for 2 mV, 5 mV, and 10 mV VOLTS/DIV scaling.
From 10 mV per division and up, the gain of the CH 1
and CH 2 Vertical Preamplifiers is set to 10 mV per
division. The 1 , 2 , 5 scaling sequence for the remain­
ing VOLTS/DIV switch settings is obtained by switch­
ing the high- and low-im pedance attenuators. Gain
of the CH 3 and CH 4 preamplifiers is controlled by
one bit each (on pin 2), since there are only two scal­
ing settings (0.1 V and 0.5 V per division) to select
(see Table 3 -5 for the gain-control bit states).
The internal circuitry of each Vertical Preamplifier is
matched for the 2 mV, 5 mV, and 10 mV gain settings
and the dc offsets. The output gain of each Preampli­
fier is adjusted by varying the com m on-m ode resis­
tance across the output pins (pin 13 to pin 14) to pro­
duce calibrated gain for each of the vertical channels.
Each Vertical Preamplifier has a trigger pickoff (pins
17, 18, 19, and 20) for supplying the internal trigger
signal to the A and B Trigger Source Selector Multi­
plexers. Capacitor coupling from pins 17 and 1‘8 to
pins 19 and 20 provides a fast-path signal into a dupli­
cate, but level-shifted, slow-path signal line. The
negative side of the differential trigger signal is term i­
nated in a capacitor to ground (from pin 19) to pro­
vide a balance for the transmission line.
Table 3-4
CH 2 INVERT Control Bit
Setting
CH 2 INV
Normal
0
INVERT
1
REV OCT 1991
3-9