Tektronix 2246 1Y, Service Manual

Page: 57 / 433

Theory of Operation—2246 1Y and 2246 Mod A Service
inhibited). Lastly, this output may be forced
high
via the Measurement Processor
interface.
T E S T : Test mode enable input (active low).
TEST is held high and not used in normal
operation. This pin is pulled high to force
normal operation, but may be pulled low to
enable the test mode. Enabling test mode
does the following:
1. Disables single sequence and B Ends A
modes, no matter what code is in the
control register.
2. Reconfigures the trigger holdoff tim er to
make it more easily testable (see control
register
description for control bits
H 4-H 0).
3. A3, A2, A1, AO = 1100 allows a negative­
going pulse on WR to reset only the
control register.
4. A3, A2, A 1, AO = 1101 allows a negative­
going pulse on WR to preset control
register bits B1-B6.
Control Register Description
The Display Sequencer internal control register is a
26-bit, serial-shift register that receives control-bit
data from the Measurement Processor. Table 3-10
lists the control signal name(s) associated with each
register bit. Bit number 1 receives the data from the
DIO pin (via the Processor Interface) after one low -
to-high transition on the WR input pin (A3 = A2 = A1
= AO = 0). Bit number 26 receives this data after 25
more low -to-high transitions on the WR input. Bit
number 26 is the m ost-significant bit position of the
internal shift register.
RD5-RD0: Data inputs to the internal RAM.
The RAM address comes from a three-bit,
binary up-counter. To write data into the
RAM, the first six bits are loaded into the
control register with the RAM data word.
With A3, A2, A 1, A0 = 0001, a negative­
going pulse on the WR input will write the
data into RAM. To set the RAM address, the
RAM load mode must be enabled. In RAM
load mode, a low -to-high transition on the
WR input (with A3, A2, A 1, A0 = 0010) will
increment the RAM address by one. There
are
eight consecutive RAM locations
(addresses 000 to 111); the. address
counter will increment to 111, then wrap
around to 000. Strobing RESET resets the
counter to 000. See the Display Sequencer
detailed description to find out what the RAM
outputs do.
Table 3-10
S hift Register 1 Control Bit Data
Bit Nr Control Signal Name(s)
1
AS2 RD5 AC3
2 AS1 RD4 AC2
3 AS0
RD3 AC1
4
ZAP RD2
5
B1S2 RD1 BC3
6 B1S1 RD0
BC2
7 B1S0 BC1
8
B1 SLOPE
BC0
9
B2S2
10 B2S1
11 B2S0
12 B2SLOPE
13 VM1
14 VM0
15 HM1
16 HM0
17 DD
18
SSE
19
B ENDS A
20
H4
21 H3
22 H2
23
HI
24 HO
25
FSEL
26
CBEN
The RD5-RD0 bits also go to the inputs of an
internal RAM comparator. The RAM outputs
are sensed by the other comparator input. If
the two inputs match, the comparator output
will be high. The RAM comparator output can
be read by the Measurement Processor
through the processor interface.
AC3-AC1: The A Trigger CPLG select bits.
BC3-BC0 are the B Trigger CPLG and SLOPE
select bits. To write these bits into the trig­
ger coupling circuits, the Measurement
Processor loads the control register as fol­
lows: Bits 1, 2, and 3 are set to AC3, AC2,
and AC1 respectively, and the A SLOPE
output is set to AC0. Bits 5, 6, 7, and 8 are
set to BC3, BC2, BC1, and BOO respectively.
The RAM load mode is enabled, the force
3-20