Tektronix 2246 1Y, Service Manual

Page: 67 / 433

Theory of Operation—2246 1Y and 2246 Mod A Service
Table 3-21
Z-Axis Switching Logic
ZM1 ZMO HD1 HDO SI
S2
S3
S4 Display Mode
0 0 0 0 1 1 1
(c)
Readout
0 0 0
1
(a)
1
(e)
1 A Sweep intensified by BUSY
0 0 1 0 1
(b)
1 1 B Sweep
0 0 1 1
(c)
1 1 1 X/Y
0 1
0
0 1 1 1
(C)
Readout
0 1 0 1
(a)
1
(d)
1 A Sweep intensified by C GATE
0 1 1 0 1 1 1 1 Blank
0 1 1 1
(c)
1 1 1 X/Y
1 0
0
0 1 1 1
(b)
Readout
1
0 0
1
(a)
1
(b)
1
A Sweep intensified by BUB
1 0 1 0 1
(b)
1 1 B Sweep
1
0
1 1
(o)
1 1 1
X/Y
1 1
0
0 1 1 1 (c)
Readout
1 1 0
1
(a)
1 1 1 A Sweep no intensified zone
1 1 1 0 1 1 1 1 Blank
1 1 1 1
(c)
1
1 1 X/Y
Notes:
(a) =
BLANK
or A G A T E ____ ____
(b) =
BLANK
or A G A T E or B U B or Z E N
(c) = BLANK
(d) =
BLANK
or A G A T E or C G A T E or Z E N
(e) =
BLANK
or A G A T E or B U S Y or Z E N
or is a logicai-or function.
ECL-to-CMOS Level Shifters
The Trigger Logic 1C, U602, is an ECL device. Its
output signal swing is the standard ECL range of
about 0.6 V. All the ECL logic devices in the 2246 1Y
and 2246 Mod A are powered from the +5 V supply
rather than a -5 V supply. The resulting output
voltage swing is from about 4.5 V to about 3.9 V
between the high and low ECL logic levels. As U602
must pass signals to the Display Sequencer 1C
(U600) at CMOS highs and lows (about 3.9 V and 0
V respectively in this application), logic level trans­
lators are required. That job is done by an identical
translator circuit for each of the three signals that
must be sent. The circuit action of U603C, Q604,
and Q605 (the A GATE translator) is described.
The single-ended A GATE output signal of U602 at
pin 14 is applied to pin 4 of U603B. With its other
input pin left open, U603B is used as a line driver
only to produce a differential output signal. That
differential signal is applied to the bases of a
differential amplifier pair of pnp transistors (Q604
and Q605). The output signal is taken across R612 in
the emitter of Q604. The em itter of Q605 is con­
nected directly to ground. When the A GATE output
of U602 is high (at 4.5 V ), the voltage applied to the
base of Q604 is 4.5 V, and the voltage on the base
of Q605 is 3.9 V. These voltage levels bias Q605 on
and Q604 off, with a resulting output level across
em itter resistor R612 of 0 V to the A GATE (active
low) input of U600. When the A GATE output of U602
goes low at the end of the sweep, the bias voltage
levels on Q604 and Q605 reverse, and Q604 is
biased on (and Q605 off). Signal current through
emitter resistor R612 develops a voltage of about
3.9 V (the unasserted level) to the A GATE input of
U600.
3-30