Tektronix 2246 1Y, Service Manual

Page: 47 / 433

Theory of Operation—2246 1Y and 2246 Mod A Service
Table 3-5
CH 3 and CH 4 Gain Control Bit
VOLTS/DIV PREAMP1
0.1 V 0
0.5 V 1
The VOLTS/DIV VAR controls for CH 1 and CH 2
(R2101 and R2103) directly vary the gain of the Ver­
tical Preamplifiers between the calibrated VOLTS/DIV
settings. The Measurement Processor detects
whether the VAR control for a channel is in or out of
its detent position; and, if out, a greater-than
symbol (>) is placed in front of the VOLTS/DIV
readout to show that the channel is uncalibrated.
Each Preamplifier produces a standing current of
about 11 mA into a common summing node. Output
of the vertical signal from a Preamplifier is controlled
by enabling signals (CH 1 EN through CH 4 EN) from
Display Logic 1C U600 (shown on Diagram 4). The
enabling signal that turns on a vertical channel signal
also enables the position signal current for that
channel through the Vertical Position Switching
circuit (either U202 or U201) into the summing node.
Delay Line Driver
The Delay Line Driver is a differential amplifier that
provides the signal amplification needed to drive
the delay line. The circuit is compensated to pro­
duce the needed circuit response at the output of
the delay line. Both sides of the differential amplifier
are identical and circuit operation of the positive side
components is described.
Transistors Q250 and Q252 are arranged as a feed­
back amplifier. The parallel combination of R250F
and R250G supplies the feedback from the emitter
of Q252 back to the base of Q250. Diode CR260
provides a one-diode voltage drop in the feedback
loop for proper biasing of the base-to-collector
junction of the input transistor (Q250). Gain of the
amplifier is set by the value of com m on-m ode re­
sistor R270 (there is a small dc voltage gain). If the
Vertical Preamplifier and Vertical Position circuit out­
put currents are exactly 11 mA (no signal and no
offsets) the feedback current is zero. Some
standing feedback current will be present if the sum
of the input currents is not exactly 55 mA. A 1 mA
current change of the input base current to Q250
produces a 41 mV change at the collector of Q252.
The no-signal dc output voltage from Q252 is
+7.5 V, and the standing current is about 15 mA.
The differential voltage between the positive and
negative side of the delay line with no signal input is
0 V +0.5 V. The differential signal voltage input to
the delay line is about 29 mV per graticule division of
deflection.
Biasing of the input transistor bases is supplied by
R262 and R264 (for Q250) and R263 and R265 (for
Q251). Two resistors in series are used to provide
the power handling needed (they are low-wattage
precision resistors). The dc voltage at the bases of
Q250 and Q251 is maintained at 7.5 V by a bias
stabilization circuit. Operational amplifier U260 com­
pares the com m on-m ode voltage at the junction of
R254 and R255 to the +7.5 V supply on its pin 3 in­
put. If the base voltage is too low, U260 raises the
com m on-m ode em itter voltage (and thereby the
base voltage) of the two input transistors.
Compensation components peak up the circuit
response to counteract the roll off effects of the
delay line. The three series-rc combinations (C272
and R272, C273 and R273, and C274 and R247)
between the emitters of Q252 and Q253 com­
pensate different frequency ranges to correctly
shape the circuit response. The series-rc circuit
between the collectors of Q252 and Q253 (C275 and
R275) damps the gain at high frequencies to prevent
oscillation. Voltage-variable capacitors CR262 and
CR263 are used to compensate for increased rolloff
at high operating tem perature. As the temperature
increases, therm istor RT201 reduces the bias across
CR282 and CR263. This causes the capacitance of
the series combination of CR262 and CR263 to in­
crease, peaking the response further. Impedance
matching and input termination of the 75 O delay line
is done by the parallel-series combination of R278,
R279, R280, and R281.
Vertical Position Switching
The Vertical Position Switching circuit consists of
buffer amplifiers for the four vertical channel position
signals (U203A, B, C, and D ), two solid state switch
arrays (U201 and U202), and a transistor paraphase
amplifier circuit (U280, Q284, and Q285).
The vertical positioning voltages from the front panel
POSITION controls are applied to the noninverting in­
puts of the four voltage-follow er buffer amplifiers
(U203A through U203D). The inputs and outputs of
the amplifiers are capacitively bypassed to eliminate
noise from the position signals. The buffered output
signals are applied to switching arrays U201 and
U202 for selection at the correct time for positioning
the displayed trace and position-related readouts.
3-10