Sun Microsystems Netra t 1120, Service Manual

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Chapter 3 Power-On Self-Test 3-9
2> <00> FPU Functional Test
2> <00> FPU Trap Test
2> <00> DMMU Primary Context Reg Test
2> <00> DMMU Secondary Context Reg Test
2> <00> DMMU TSB Reg Test
2> <00> DMMU Tag Access Reg Test
2> <00> DMMU VA Watchpoint Reg Test
2> <00> DMMU PA Watchpoint Reg Test
2> <00> IMMU TSB Reg Test
2> <00> IMMU Tag Access Reg Test
2> <00> DMMU TLB Tag Access Test
2> <00> DMMU TLB RAM Access Test
0> <00> CPU Addr Align Trap Test
0> <00> DMMU Access Priv Page Test
0> <00> DMMU Write Protected Page Test
0> <1f> Init Psycho
0> <1f> Pri CE ECC Error Test
0> <1f> Pri UE ECC Error Test
0> <1f> Pri 2 bit w/ bit hole UE ECC Err Test
0> <1f> Pri 3 bit UE ECC Err Test
0> <1f> Streaming DMA UE ECC Rd Err Ebus Test
0> <1f> Streaming DMA CE ECC Rd Err Ebus Test
0> <1f> Streaming DMA CE ECC Rd Err Lpbk Test
0> <1f> Consistent DMA UE ECC Rd Error Ebus Test
0> <1f> Consistent DMA UE ECC R/M/W Err Ebus Test
0> <1f> Consistent DMA UE ECC R/M/W Err Lpbk Test
0> <1f> Consistent DMA CE ECC Rd Err Ebus Test
0> <1f> Consistent DMA CE ECC Rd Err Lpbk Test
0> <1f> Consistent DMA CE ECC R/M/W Err Ebus Test
0> <1f> Consistent DMA CE ECC R/M/W Err Lpbk Test
0> <1f> Consistent DMA Wr Data Parity Err Lpbk Test
0> <1f> Pass-Thru DMA UE ECC Rd Err Ebus Test
0> <1f> Pass-Thru DMA UE ECC R/M/W Err Ebus Test
0> <1f> Pass-Thru DMA UE ECC R/M/W Err Lpbk Test
0> <1f> Pass-Thru DMA CE ECC Rd Err Ebus Test
0> <1f> Pass-Thru DMA CE ECC Rd Err Lpbk Test
0> <1f> Pass-Thru DMA CE ECC R/M/W Err Ebus Test
0> <1f> Pass-Thru DMA CE ECC R/M/W Err Lpbk Test
0> <1f> Pass-Thru DMA Write Data Parity Err, Lpbk Test
0> <1f> Init Psycho
0> <1f> Mondo Generate Interrupt Test
0> <1f> Timer Interrupt Test
0> <1f> Timer Interrupt w/ periodic Test
0> <1f> Psycho Stream Buff A Flush Sync Test
0> <1f> Psycho Stream Buff B Flush Sync Test
0> <1f> Psycho Stream Buff A Flush Invalidate Test
0> <1f> Psycho Stream Buff B Flush Invalidate Test
CODE EXAMPLE 3-1 diag-level
Variable Set to
max
(Continued)