Sun Microsystems Netra t 1120, Service Manual

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Chapter 3 Power-On Self-Test 3-7
2> <00> Icache Next Test
2> <00> Icache Predecode Test
0> <1f> Init Psycho
0> <1f> PIO Read Error, Master Abort Test
0> <1f> PIO Read Error, Target Abort Test
0> <1f> PIO Write Error, Master Abort Test
0> <1f> PIO Write Error, Target Abort Test
0> <1f> Timer Increment Test
0> <1f> Consistent DMA UE ECC Rd Err Lpbk Test
0> <1f> Pass-Thru DMA UE ECC Rd Err Lpbk Test
0> <00> Copy Post to Memory
0> <00> Ecache Thrash Test
0> <00> Init Memory
0> <00> Memory Addr w/ Ecache Test
0>INFO: 0MB Bank 0
0>INFO: 0MB Bank 1
0>INFO: 0MB Bank 2
0>INFO: 128MB Bank 3
0> <00> Block Memory Addr Test
0>INFO: 0MB Bank 0
0>INFO: 0MB Bank 1
0>INFO: 0MB Bank 2
0>INFO: 128MB Bank 3
0> <00> ECC Memory Addr Test
0>INFO: 0MB Bank 0
0>INFO: 0MB Bank 1
0>INFO: 0MB Bank 2
0>INFO: 128MB Bank 3
0> <00> Memory Status Test
0>INFO: 0MB Bank 0
0>INFO: 0MB Bank 1
0>INFO: 0MB Bank 2
0>INFO: 128MB Bank 3
0> <00> V9 Instruction Test
0> <00> CPU Tick and Tick Compare Reg Test
0> <00> CPU Soft Trap Test
0> <00> CPU Softint Reg and Int Test
2> <00> V9 Instruction Test
2> <00> CPU Tick and Tick Compare Reg Test
0> <1f> Init Psycho
0> <1f> Psycho Cntl and UPA Reg Test
0> <1f> Psycho DMA Scoreboard Reg Test
0> <1f> Psycho Perf Cntl Reg Test
0> <1f> PIO Decoder and BCT Test
0> <1f> PCI Byte Enable Test
0> <1f> Counter/Timer Limit Regs Test
0> <1f> Timer Reload Test
CODE EXAMPLE 3-1 diag-level
Variable Set to
max
(Continued)