SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 61
Version 1.9
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SYSTEM OPERATION MODE
4.1 OVERVIEW
The chip builds in four operating mode for difference clock rate and power saving reason. These modes control
oscillators, op-
code operation and analog peripheral devices’ operation.
Normal mode
Sleep mode
Deep sleep mode
Deep Power-down mode
4.2 NORMAL MODE
In Normal mode, the ARM Cortex-M0 core, memories, and peripherals are clocked by the system clock. The
register controls which peripherals are running.
Selected peripherals have individual peripheral clocks with their own clock dividers in addition to the system clock. The
peripheral clocks can be disabled respectively.
The power to various analog blocks
(IHRC, EHS X’TAL, ELS X’TAL, PLL, Flash, LVD, Codec, Comparator) can be
controlled at any time individually through the enable bit of all blocks.
4.3 LOW-POWER MODES
There are three special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep power-down
mode. The
register controls which mode is going to entered.
The CPU clock rate may also be controlled as needed by changing clock sources, re-configuring PLL values, and/or
altering the system clock divider value. This allows a trade-off of power versus processing speed based on application
requirements.
Run-time power control allows disable the clocks to individual on-chip peripherals, allowing fine tuning of power
consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected
peripherals have their own clock divider for power control.
Note: 1. The debug mode is not supported in Deep-sleep and Deep Power-down mode.
2. The pins which are not pin-out shall be set correctly to decrease power consumption in low-
power modes. Strongly recommended to set these pins as input pull-up.
4.3.1 SLEEP MODE
In Sleep mode, the system clock to the ARM Cortex-M0 core is stopped and execution of instructions is suspended.
Peripheral functions, if selected to be clocked in
register, continue operation during Sleep mode
and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used
by the processor itself, memory systems and related controllers, and internal buses.
The power state of the analog blocks
(IHRC, EHS X’TAL, ELS X’TAL, PLL, Flash, LVD, Codec, Comparator) is