SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 113
Version 1.9
11.5 I2C MASTER MODES
11.5.1 MASTER TRANSMITTER MODE
S
Transmit Address
ACK_=0
1
A7
2
A6
3
A5
4
A4
5
A3
6
A2
7
A1
8
9
ACK_
1
2
D6
3
D5
4
D4
5
D3
6
D2
7
D1
8
D0
9
P
SDA
SCL
Transmission Data
R/W=0
Write 1 to STA bit,
START condition begins
STA=0
D7
Write address and TXDATA
Start transmit
From Slave
SCL held Low
ACK_STAT=1
SDA
SCL
1st-bit
Repeat Start
Write 1 to STA bit
Falling edge of ninth clock,
End of transmission
SDA=1, SCL=1
Complete of Start bit
Write to TXDATA
11.5.2 MASTER RECEIVER MODE
S
Transmit Address to Slave
ACK_=0
1
A7
2
A6
3
A5
4
A4
5
A3
6
A2
7
A1
8
9
ACK_
1
2
D6
3
D5
4
D4
5
D3
6
D2
7
D1
8
SDA
SCL
Receiving Data from Slave
R/W=1
Write 1 to STA bit
START condition begins
STA=0
D7
Write address and TXDATA
Start transmit
From Slave
1
2
D6
3
D5
4
D4
5
D3
6
D2
7
D1
P
9
D6
ACK_
9
8
D0
D0
Write 1 to ACK bit
Start Acknowledge sequence
ACK from Master
Receiving Data from Slave
ACK_ is not
sent
Write 1 to STO bit
Master terminal transfer
Data shifted in failing edgeof SCL
Write 1 to ACK bit
Start Acknowledge sequence
11.5.3 ARBITRATION
In the master transmitter mode, the arbitration logic checks that every transmitted logic 1 actually appears as logic 1 on
the I2C bus. If another device on the bus overrules a logic 1 and pulls the SDA line low, arbitration is lost, and the I2C
block immediately changes from master transmitter to slave receiver. The I2C block will continue to output clock pulses
(on SCL) until transmission of the current serial byte is complete.
Arbitration may also be lost in the master receiver mode. Loss of arbitration in this mode can only occur while the I2C
block is returning a “not acknowledge” to the bus. Arbitration is lost when another device on the bus pulls this signal low.
Since this can occur only at the end of a serial byte, the I2C block generates no further clock pulses.