SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 56
Version 1.9
3.4 SYSTEM CONTROL REGISTERS 1
Base Address: 0x4005 E000
3.4.1 AHB Clock Enable register (SYS1_AHBCLKEN)
Address Offset: 0x00
The SYS_AHBCLKEN register enables the AHB clock to individual system and peripheral blocks.
Note:
1. When the clock is disabled, the peripheral register values may not be readable by SW and the
value returned is always 0x0.
2. HW will replace GPIO with CLKOUT function directly if CLKOUTSEL is Not 0.
Bit
Name
Description
Attribute
Reset
31
Reserved
R
0
30:28
CLKOUTSEL[2:0]
Clock output source
000: Disable
001: HCLK
010: PLL clock output
011: ILRC clock
100: IHRC clock
101: ELS clock
110: EHS clock
111: AUEHS clock
R/W
0
27:25
Reserved
R
0
24
WDTCLKEN
Enables clock for WDT.
0: Disable
1: Enable
R/W
1
23
RTCCLKEN
Enables clock for RTC.
0: Disable
1: Enable
R/W
0
22
I2SCLKEN
Enables clock for I2S.
0: Disable
1: Enable
R/W
0
21
I2C0CLKEN
Enables clock for I2C0.
0: Disable
1: Enable
R/W
0
20
I2C1CLKEN
Enables clock for I2C1.
0: Disable
1: Enable
R/W
0
19:18
Reserved
R
0
17
UART1CLKEN
Enables clock for UART1.
0: Disable
1: Enable
R/W
0
16
UART0CLKEN
Enables clock for UART0.
0: Disable
1: Enable
R/W
0
15:14
Reserved
R
0
13
SSP1CLKEN
Enables clock for SSP1.
0: Disable
1: Enable
R/W
0
12
SSP0CLKEN
Enables clock for SSP0.
0: Disable
1: Enable
R/W
0
11
CMPCLKEN
Enables clock for Comparator.
0: Disable
1: Enable
R/W
0
