SONIX SN32F107, User Manual

Page: 71 / 184

SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 71
Version 1.9
5.3.8 GPIO Port n Raw Interrupt Status register (GPIOn_RIS) (n=0,1,2,3)
Address offset: 0x1C
This register indicates the status for GPIO control raw interrupts. A GPIO interrupt is sent to the interrupt controller if
the corresponding bit in GPIOn_IE register is set.
Bit Name Description Attribute Reset
31:16
Reserved R 0
15:0 IF[15:0]
GPIO raw interrupt flag (x = 0 to 15).
0: No interrupt on Pn.x
1: Interrupt requirements met on Pn.x.
R 0
5.3.9 GPIO Port n Interrupt Clear register (GPIOn_IC) (n=0,1,2,3)
Address offset: 0x20
Bit Name Description Attribute Reset
31:16
Reserved R 0
15:0 IC[15:0]
Selects interrupt flag on pin x to be cleared (x = 0 to 15).
0: No effect
1: Clear interrupt flag on Pn.x
W 0
5.3.10 GPIO Port n Bits Set Operation register (GPIOn_BSET) (n=0,1,2,3)
Address offset: 0x24
In order for SW to set GPIO bits without affecting any other pins in a single write operation, the GPIO bit is set if the
corresponding bit in the GPIOn_BSET register is set.
Bit Name Description Attribute Reset
31:16 Reserved R 0
15:0
BSET[15:0]
Bit Set enable (x = 0 to 15)
0: No effect on Pn.x
1: Set Pn.x to “1”
W 0
5.3.11 GPIO Port n Bits Clear Operation register (GPIOn_BCLR) (n=0,1,2,3)
Address offset: 0x28
In order for SW to clear GPIO bits without affecting any other pins in a single write operation, the GPIO bit is cleared if
the corresponding bit in this register is set.
Bit Name Description Attribute Reset
31:16 Reserved R 0
15:0 BCLR[15:0]
Bit clear enable (x = 0 to 15)
0: No effect on Pn.x
1: Clear Pn.x.
W 0
5.3.12 GPIO Port n Open-Drain Control register (GPIOn_ODCTRL) (n=0,1,2,3)
Address offset: 0x2C
Several I/Os have built-in open-drain function and must be set as output mode when enable open-drain function.
Open-drain external circuit is as following.