SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 62
Version 1.9
determined by the enable bit of all blocks.
The processor state and registers, peripheral registers, and internal SRAM values are maintained and the logic levels
of the pins remain static.
Wake up the chip from Sleep mode by an interrupt occurs.
The RESET pin has keep functionality in Sleep mode.
The Sleep mode is entered by using the following steps:
1. Write 1 to SLEEPEN bit in
2. Execute ARM Cortex-M0 WFI instruction.
4.3.2 DEEP-SLEEP MODE
In Deep-sleep mode, the system clock to the ARM Cortex-M0 core is stopped, and execution of instructions is
suspended.
The clock to the peripheral functions are stopped because the power state of oscillators are powered down, the clock
source are stopped,
except RTC low speed clock source (ELS X’TAL, ILRC) if used.
Note: User SHALL decide to power down RTC low speed cloc
k source (ELS X’TAL, ILRC oscillator) or not
if RTC is enabled.
The processor state and registers, peripheral registers, and internal SRAM values are maintained and the logic levels
of the pins remain static.
Wake up the chip from Deep-sleep mode by anyone of GPIO port pins (P0~P3) interrupt trigger or RTC interrupt.
The RESET pin has keep functionality in Deep-sleep mode.
The Deep-sleep mode is entered by using the following steps:
1. Write 1 to DSLEEPEN bit in
2. Execute ARM WFI instruction.
The advantage of the Deep-sleep mode is that can power down clock generating blocks such as oscillators and PLL,
thereby gaining far greater dynamic power savings over Sleep mode. In addition, the Flash can be powered down in
Deep-sleep mode resulting in savings in static leakage power, however at the expense of longer wake-up times for the
Flash memory.
4.3.3 DEEP POWER-DOWN (DPD) MODE
In Deep power-down mode, power (Turn off the on-chip voltage regulator) and clocks are shut off to the entire chip with
the exception of the DPDWAKEUP pin. DPDWAKEUP pin must be pulled HIGH externally to enter Deep power-down
mode and pulled LOW to exit Deep power-down mode.
The processor state and registers, peripheral registers, and internal SRAM values are not retained. However, the chip
can retain data in four BACKUP registers.
Wakes up the chip from Deep power-down mode by pulling the DPDWAKEUP pin LOW (Turn on the on-chip voltage
regulator. When the core voltage reaches the power-on-reset (POR) trip point, a system reset will be triggered and the
chip re-boots).
The RESET pin has no functionality in Deep power-down mode.
