SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 83
Version 1.9
7
7
7
32-BIT TIMER WITH CAPTURE
FUNCTION
7.1 OVERVIEW
Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and can
optionally generate interrupts or perform other actions at specified timer values based on four match registers. Each
counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally
generating an interrupt.
In PWM mode, up to two match registers can be used to provide a single-edge controlled PWM output on the match
output pins.
7.2 FEATURES
Two 32-bit counter/timers with a programmable 16-bit prescale value.
Counter or timer operation
Two 32-bit capture channels that can take a snapshot of the timer value when an input signal transitions. A
capture event may also optionally generate an interrupt.
The timer and the prescale value may be configured to be cleared on a designated capture event. This feature
permits easy pulse-width measurement by clearing the timer on the leading edge of an input pulse and capturing
the timer value on the trailing edge.
For each timer, four 32-bit match registers that allow:
–
Continuous operation with optional interrupt generation on match.
–
Stop timer on match with optional interrupt generation.
–
Reset timer on match with optional interrupt generation.
– C
onfigured as PWM allowing using up to two match outputs as single edge controlled PWM outputs.
For each timer, up to two PWM outputs corresponding to match registers with the following capabilities:
–
Set LOW on match.
–
Set HIGH on match.
–
Toggle on match.
–
Do nothing on match.
7.3 PIN DESCRIPTION
Pin Name
Type
Description
GPIO Configuration
CT32Bn_CAP0
I
Capture channel input 0
Depends on GPIOn_CFG
CT32Bn_PWMx
O
Output channel x of Match/PWM output.
