SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 52
Version 1.9
3.3.3 Clock Source Status register (SYS0_CSST)
Address Offset: 0x08
Bit
Name
Description
Attribute
Reset
31:9
Reserved
R
0
8
AUEHSRDY
Audio external high-speed clock ready flag
0: AUEHS oscillator not ready
1: AUEHS oscillator ready
R
0
7
Reserved
R
0
6
PLLRDY
PLL clock ready flag
0: PLL unlocked
1: PLL locked
R
0
5
Reserved
R
0
4
EHSRDY
External high-speed clock ready flag
0: EHS oscillator not ready
1: EHS oscillator ready
R
0
3
Reserved
R
0
2
ELSRDY
External low-speed clock ready flag
0: EHS oscillator not ready
1: EHS oscillator ready
R
0
1
Reserved
R
0
0
IHRCRDY
IHRC ready flag
0: IHRC not ready
1: IHRC ready
R
1
3.3.4 System Clock Configuration register (SYS0_CLKCFG)
Address Offset: 0x0C
Bit
Name
Description
Attribute
Reset
31:7
Reserved
R
0
6:4
SYSCLKST[2:0]
System clock switch status
Set and cleared by HW to indicate which clock source is used as system
clock.
000: IHRC is used as system clock
001: ILRC is used as system clock
010: EHS X’TAL is used as system clock
011: ELS X’TAL is used as system clock
100: PLL is used as system clock
Other: Reserved
R
0
3
Reserved
R
0
2:0
SYSCLKSEL[2:0]
System clock switch
Set and cleared by SW.
000: IHRC
001: ILRC
010: EHS X’TAL
011: ELS X’TAL
100: PLL output
Other: Reserved
R/W
0
3.3.5 AHB Clock Prescale register (SYS0_AHBCP)
Address Offset: 0x10
Bit
Name
Description
Attribute
Reset
31:4
Reserved
R
0
