SONIX SN32F107, User Manual

Page: 90 / 184

SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 90
Version 1.9
1:0 CAP0RE
Capture/Reset on CT32Bn_CAP0 signal rising edge.
0: Disable
1: Enable a sequence of 0 then 1 on CT32Bn_CAP0 signal will cause
CAP0 to be loaded with the contents of TC.
2: Enable a sequence of 0 then 1 on CT32Bn_CAP0 signal will reset the
TC.
3: Reserved.
R/W 0
7.7.9 CT32Bn Capture 0 register (CT32Bn_CAP0) (n=0,1)
Address Offset: 0x2C
Each Capture register is associated with a device pin and may be loaded with the counter/timer value when a specified
event occurs on that pin. The settings in the Capture Control register determine whether the capture function is
enabled, and whether a capture event happens on the rising edge of the associated pin, the falling edge, or on both
edges.
Bit Name Description Attribute Reset
31:0 CAP0[31:0] Timer counter capture value R 0
7.7.10 CT32Bn External Match register (CT32Bn_EM) (n=0,1)
Address Offset: 0x30
The External Match register provides both control and status of the external match pins CT32Bn_PWMCTRL[1:0].
If the match outputs are configured as PWM output, the function of the external match registers is determined by the
PWM rules .
Bit Name Description Attribute Reset
31:8 Reserved R 0
7:6 EMC1[1:0]
Determines the functionality of CT32Bn_PWM1.
00: Do Nothing.
01: CT32Bn_PWM1 pin is LOW
10: CT32Bn_PWM1 pin is HIGH.
11: Toggle CT32Bn_PWM1.
R/W 0
5:4 EMC0[1:0]
Determines the functionality of CT32Bn_PWM0.
00: Do Nothing.
01: CT32Bn_PWM0 pin is LOW
10: CT32Bn_PWM0 pin is HIGH
11: Toggle CT32Bn_PWM0.
R/W 0
3:2 Reserved R 0
1
EM1
When the TC and MR1 are equal, this bit will act according to EMC1 bits,
and also drive the state of CT32Bn_PWM1 output.
R/W 0
0 EM0
When the TC and MR0 are equal, this bit will act according to EMC0 bits,
and also drive the state of CT32Bn_PWM0 output.
R/W 0
7.7.11 CT32Bn PWM Control register (CT32Bn_PWMCTRL) (n=0,1)
Address Offset: 0x34
The PWM Control register is used to configure the match outputs as PWM outputs. Each match output can be
independently set to perform either as PWM output or as match output whose function is controlled by
CT32Bn_EM
register.
For each timer, a maximum of three single edge controlled PWM outputs can be selected on the
CT32Bn_PWMCTRL[3:0] outputs. One additional match register determines the PWM cycle length. When a match
occurs in any of the other match registers, the PWM output is set to HIGH. The timer is reset by the match register that
is configured to set the PWM cycle length. When the timer is reset to zero, all currently HIGH match outputs configured
as PWM outputs are cleared.
Bit Name Description Attribute Reset
31:22 Reserved R 0
21
PWM1IOEN
CT32Bn_PWM1/GPIO selection bit
R/W 0