SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 131
Version 1.9
Note:
1. The
break interrupt (BI) is associated with the character at the top of the UARTn_RB FIFO.
2. The
framing error (FE) is associated with the character at the top of the UARTn_RB FIFO.
3.
The
parity error (PE) is associated with the character at the top of the UARTn_RB FIFO.
Bit
Name
Description
Attribute
Reset
31:8
Reserved
R
0
7
RXFE
Error in RX FIFO flag.
RXFE =1 when a character with a RX error such as framing error, parity
error, or break interrupt, is loaded into the UARTn_RB register. This bit is
cleared when the UARTn_LS register is read and there are no subsequent
errors in the UART FIFO.
0: UARTn_RB register contains no UART RX errors or FIFOEN=0
1: UARTn_RB register contains at least one UART RX error.
R
0
6
TEMT
Transmitter Empty flag
TEMT=1 when both THR and TSR are empty; TEMT is cleared when
either the TSR or the THR contain valid data.
0: THR and/or TSR contains valid data.
1: THR and TSR are empty.
R
1
5
THRE
Transmitter Holding Register Empty flag
THRE indicates that the UART is ready to accept a new character for
transmission. In addition, this bit causes the UART to issue THRE interrupt
to if THREIE=1. THRE=1 when a character is transferred from the THR
into the TSR. The bit is reset to logic 0 concurrently with the loading of the
Transmitter Holding Register by the CPU.
0: THR contains valid data.
1: THR (TX FIFO) is empty.
R
1
4
BI
Break Interrupt flag.
When RXD1 is held in the spacing state (all zeros) for one full character
transmission (start, data, parity, stop), a break interrupt occurs. Once the
break condition has been detected, the receiver goes idle until RXD1 goes
to marking state (all ones). A UARTn_LS register read clears BI bit. The
time of break detection is dependent on FIFOEN bit in UARTn_FIFOCTRL
register.
0: Break interrupt status is inactive.
1: Break interrupt status is active.
R
0
3
FE
Framing Error flag.
When the stop bit of a received character is a logic 0, a framing error
occurs. A UARTn_LS register read clears FE bit. The time of the framing
error detection is dependent on FIFOEN bit in UARTn_FIFOCTRL
register.
Upon detection of a framing error, the RX will attempt to re-synchronize to
the data and assume that the bad stop bit is actually an early start bit.
However, it cannot be assumed that the next received byte will be correct
even if there is no Framing Error.
0: Framing error status is inactive.
1: Framing error status is active.
R
0
2
PE
Parity Error flag.
When the parity bit of a received character is in the wrong state, a parity
error occurs. A UARTn_LS register read clears PE bit. Time of parity error
detection is dependent on FIFOEN bit in UARTn_FIFOCTRL register.
0: Parity error status is inactive.
1: Parity error status is active.
R
0
1
OE
Overrun Error flag.
The overrun error condition is set as soon as it occurs. A UARTn_LS
register read clears OE bit. OE=1 when UART RSR has a new character
assembled and the UARTn_RB FIFO is full. In this case, the UARTn_RB
FIFO will not be overwritten and the character in the UARTn_RS register
will be lost.
0: Overrun error status is inactive.
1: Overrun error status is active.
R
0
0
RDR
Receiver Data Ready flag
RDR=1 when the UARTn_RB FIFO holds an unread character and is
R
0
