SONIX SN32F107 User Manual Download Page 14

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SN32F100 Series

32-Bit Cortex-M0 Micro-Controller

SONiX TECHNOLOGY CO., LTD

Page 14

Version 1.9



Features Selection Table

Chip

ROM

RAM

Boot

Loader

CPU

(Max

MHz)

UART

SPI

I2C

I2S

TIMER

PWM

16-bit

Σ-δ

ADC

16-bit

Σ-δ

DAC

CMP

GPIO

with

Wakeup

Package

SN32F107F

64KB

8KB

4KB

16-bit x 2
32-bit x 2

LQFP48

SN32F108F

64KB

8KB

4KB

16-bit x 2
32-bit x 2

LQFP64

SN32F109F

64KB

8KB

4KB

16-bit x 2
32-bit x 2

LQFP80

Summary of Contents for SN32F107

Page 1: ...igned intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which...

Page 2: ...diagram 4 Update Code Option Table 5 Update High level and Low level input voltage Spec 6 Update P0 14 DPDWAKEUP pin description 1 5 2014 02 27 1 Update Electrical characteristics 2 Update Code Secur...

Page 3: ...STICK_LOAD 29 2 2 3 3 System Tick Timer Current Value register SYSTICK_VAL 30 2 2 3 4 System Tick Timer Calibration Value register SYST_CALIB 30 2 3 NESTED VECTORED INTERRUPT CONTROLLER NVIC 31 2 3 1...

Page 4: ...YSTAL CERAMIC 46 3 2 3 3 Audio External High speed AUEHS Clock 47 3 2 3 4 External Low speed ELS Clock 47 3 2 3 5 CRYSTAL 47 3 2 3 6 Bypass Mode 48 3 2 4 SYSTEM CLOCK SYSCLK SELECTION 49 3 2 5 CLOCK O...

Page 5: ...DE 67 5 3 GPIO REGISTERS 68 5 3 1 GPIO Port n Data register GPIOn_DATA n 0 1 2 3 68 5 3 2 GPIO Port n Mode register GPIOn_MODE n 0 1 2 3 68 5 3 3 GPIO Port n Configuration register GPIOn_CFG n 0 1 2 3...

Page 6: ...nterrupt Status register CT16Bn_RIS n 0 1 82 6 7 13 CT16Bn Timer Interrupt Clear register CT16Bn_IC n 0 1 82 7 7 7 32 BIT TIMER WITH CAPTURE FUNCTION 83 7 1 OVERVIEW 83 7 2 FEATURES 83 7 3 PIN DESCRIP...

Page 7: ...RATION 97 9 4 BLOCK DIAGRAM 98 9 5 RTC REGISTERS 99 9 5 1 RTC Control register RTC_CTRL 99 9 5 2 RTC Clock Source Select register RTC_CLKS 99 9 5 3 RTC Interrupt Enable register RTC_IE 99 9 5 4 RTC Ra...

Page 8: ...13 11 5 1 MASTER TRANSMITTER MODE 113 11 5 2 MASTER RECEIVER MODE 113 11 5 3 ARBITRATION 113 11 6 I2C SLAVE MODES 114 11 6 1 SLAVE TRANSMITTER MODE 114 11 6 2 SLAVE RECEIVER MODE 114 11 7 MONITOR MODE...

Page 9: ...2 7 8 UART n Line Control register UARTn_LC n 0 1 130 12 7 9 UART n Line Status register UARTn_LS n 0 1 130 12 7 10 UART n Scratch Pad register UARTn_SP n 0 1 132 12 7 11 UART n Auto baud Control regi...

Page 10: ...5 ADC Setting 5 register ADC_SET5 147 13 7 6 ADC Setting 6 register ADC_SET6 147 13 7 7 ADC Setting 7 register ADC_SET7 147 13 7 8 ADC Setting 8 register ADC_SET8 148 13 7 9 ADC Setting 9 register AD...

Page 11: ...1 OVERVIEW 155 14 2 COMPARATOR OPERATION 156 14 3 COMPARATOR APPLICATION NOTICE 157 14 4 COMPARATOR CONTROL REGISTERS 157 14 4 1 Comparator Control register CMPM 157 14 4 2 Comparator Interrupt Enable...

Page 12: ...WD PINS 167 1 1 17 7 7 DEVELOPMENT TOOL 168 17 1 SN LINK V2 169 17 2 SN32F100 STARTER KIT 170 17 2 1 SN32F100 Start Kit V1 0 170 17 2 2 SN32F100 Start Kit V1 1 V1 2 172 1 1 18 8 8 ELECTRICAL CHARACTER...

Page 13: ...ystem tick timer Two UART controllers with fractional baud rate 24 bit timer generation The system tick timer clock is fixed to the frequency of Two SPI controllers with SSP features and multi the sys...

Page 14: ...RAM Boot Loader FCPU Max MHz UART SPI I2C I2S TIMER PWM 16 bit ADC 16 bit DAC CMP GPIO with Wakeup Package SN32F107F 64KB 8KB 4KB 50 1 1 2 16 bit x 2 32 bit x 2 4 1 1 8 32 LQFP48 SN32F108F 64KB 8KB 4...

Page 15: ...ET ARM CORTEX M0 CLOCK GENERATION FLASH ROM 64KB SRAM 8KB SYS PMU POWER CONTROL SYSTEM FUNCTIONS SPI1 I2C0 UART 0 SPI0 UART 1 POWER REGULATOR ILRC 16KHz IHRC 12MHz LVD Clocks Controls AHB LITE BUS AHB...

Page 16: ...ck source I2C0 Clock Prescaler 1 2 4 8 16 I2C0_PCLK AHB clock for ADC I2C0CLKEN I2C0 register block I2C0 clock source CT32B1 Clock Prescaler 1 2 4 8 16 CT32B1_PCLK AHB clock for CT32B1 CT32B1CLKEN CT3...

Page 17: ...1 CT16B1_CAP0 4 57 P2 8 CM8 P0 0 URXD0 5 56 P2 7 CM7 P0 1 UTXD0 6 55 P2 6 CM6 P0 2 SCL0 7 54 P2 5 CM5 P0 3 SDA0 8 53 P2 4 CM4 P0 4 SCK0 PGDCLK 9 52 P2 3 CM3 P0 5 SEL0 PGDIN 10 51 P2 2 CM2 P0 6 MISO0 O...

Page 18: ...0 5 44 P2 4 CM4 P0 1 UTXD0 6 43 P2 3 CM3 P0 2 SCL0 7 42 P2 2 CM2 P0 3 SDA0 8 41 P2 1 CM1 P0 4 SCK0 PGDCLK 9 40 P2 0 CM0 P0 5 SEL0 PGDIN 10 39 P1 13 XTALOUT P0 6 MISO0 OTPCLK 11 38 P1 12 XTALIN P0 7 MO...

Page 19: ...XTALOUT P0 3 SDA0 4 33 P1 12 XTALIN P0 4 SCK0 PGDCLK 5 32 P1 1 AUXTALIN P0 5 SEL0 PGDIN 6 31 P1 0 AUXTALOUT P0 6 MISO0 OTPCLK 7 30 P1 11 LXTALOUT P0 7 MOSI0 VR_DOUT 8 29 P1 10 LXTALIN P0 12 SWCLK 9 28...

Page 20: ...D0 Receiver input for UART0 P0 1 UTXD0 I O P0 1 General purpose digital input output pin with high current sink driver UTXD0 Transmitter output for UART0 P0 2 SCL0 I O P0 2 General purpose digital inp...

Page 21: ...utput pin RESET external Reset input P1 0 AUXTALOUT I O P1 0 General purpose digital input output pin AUXTALOUT External high speed X tal output pin for audio P1 1 AUXTALIN I O P1 1 General purpose di...

Page 22: ...speed X tal output pin P2 0 CMP I O P2 0 General purpose digital input output pin CMP Comparator channel 0 P2 1 CM1 I O P2 1 General purpose digital input output pin CM1 Comparator channel 1 P2 2 CM2...

Page 23: ...digital input output pin CM16 Comparator channel 16 P3 1 CM17 I O P3 1 General purpose digital input output pin CM17 Comparator channel 17 P3 2 CM18 I O P3 2 General purpose digital input output pin C...

Page 24: ...neral purpose digital input output pin with high current sink driver URXD1 Receiver data input for UART1 CT16B0_CAP0 Capture input 0 for CT16B0 P3 13 UTXD1 CT16B1_CAP0 I O P3 13 General purpose digita...

Page 25: ...t Bus GPIOPn_MODE RPD GPIOn_CFG GPIOPn_MODE Specific Input Bus Specific Input Function Control Bit Specific Output Function Control Bit Some specific functions switch I O direction directly not throug...

Page 26: ...Specific Output Function Control Bit Some specific functions switch I O direction directly not through GPIOn_MODE register Analog IP Input Terminal Bi direction I O Pin Shared with Specific Analog Out...

Page 27: ...2000 0x4001 4000 WDT 0x4001 6000 0x4001 8000 0x4001 C000 Reserved Reserved Reserved Reserved I2C0 0x4004 4000 0x4004 6000 0x4004 8000 GPIO2 GPIO3 GPIO0 GPIO1 Reserved 0x4008 0000 0xE000 0000 0xE010 0...

Page 28: ...e a fixed 10 ms time interval between interrupts The system tick timer is enabled through the SysTick control register The system tick timer clock is fixed to the frequency of the system clock The blo...

Page 29: ...CLKSOURCE Selects the SysTick timer clock source 0 reference clock 1 system clock Fixed R 1 1 TICKINT System Tick interrupt enable 0 Disable the System Tick interrupt 1 Enable the System Tick interru...

Page 30: ...0x7E7F35 2 2 3 4 System Tick Timer Calibration Value register SYST_CALIB Address 0xE000 E01C Refer to Cortex M0 Spec Bit Name Description Attribute Reset 31 NOREF Indicates the reference clock to M0...

Page 31: ...dFault_Handler All class of fault 0x0000 000C 4 10 Reserved Reserved Reserved 11 Settable SVCCall 0x0000 002C 12 13 Reserved Reserved Reserved 14 Settable PendSV 0x0000 0038 15 Settable SysTick 0x0000...

Page 32: ...led Bit Name Description Attribute Reset 31 0 CLRENA 31 0 Interrupt clear enable bits Write 0 No effect 1 Disable interrupt Read 0 Interrupt disabled 1 Interrupt enabled R W 0 2 3 2 3 IRQ0 31 Interrup...

Page 33: ...alue 192 to the register R W 0 15 8 PRI_ 4 n 1 Each priority field holds a priority value 0 192 The lower the value the greater the priority of the corresponding interrupt The processor implements onl...

Page 34: ...SN32F100 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 34 Version 1 9 0 Reserved R 0...

Page 35: ...CHNOLOGY CO LTD Page 35 Version 1 9 2 5 CODE OPTION TABLE Address 0x1FFF 2000 Bit Name Description Attribute Reset 31 16 Code Security 15 0 Code Security 0xFFFF CS0 0x5A5A CS1 0xA5A5 CS2 0x55AA CS3 R...

Page 36: ...ster LR It stores the return information for subroutines function calls and exceptions PC R15 The Program Counter PC It contains the current program address On reset the processor loads the PC with th...

Page 37: ...but the crystal type is longer Under client terminal application users have to take care of the power on reset time for the master terminal requirement The reset timing diagram is as following VDD VS...

Page 38: ...hdog timer function Note Please refer to the WATCHDOG TIMER about watchdog timer detail information 3 1 3 BROWN OUT RESET 3 1 3 1 BROWN OUT DESCRIPTION The brown out reset is a power dropping conditio...

Page 39: ...ifferent system executing rates have different system minimum operating voltage The electrical characteristic section shows the system voltage to executing rate relationship Vdd V System Rate Fcpu Sys...

Page 40: ...urn normal mode If the system reset by watchdog and the power is still in dead band the system reset sequence won t be successful and the system stays in reset status until the power return to normal...

Page 41: ...it operation makes a slow rising signal into reset pin as power up The reset signal is slower than VDD power up timing and system occurs a power on signal from the timing difference Note The reset cir...

Page 42: ...0 7V the C terminal of the PNP transistor outputs high voltage and MCU operates normally When VDD is below Vz 0 7V the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode Dec...

Page 43: ...error occurrence as power dropping When power drops below the reset detect voltage the system reset would be triggered and then system executes reset sequence That makes sure the system work well und...

Page 44: ...speed clock The high speed clock is generated from the external oscillator on chip PLL circuit The low speed clock is generated from on chip low speed RC oscillator circuit ILRC 16 KHz 3 2 1 INTERNAL...

Page 45: ...phase frequency detector is also monitored by the lock detector to signal when the PLL has locked on to the input clock The PLL settling time is 100 s PFD LPF VCO DIV M DIV P Fclkout Fvco Fclkin DIV...

Page 46: ...are driven by XIN XOUT pins For high normal low frequency the driving currents are different MCU VCC GND C 20pF XIN XOUT VDD VSS C 20pF CRYSTAL Note Connect the Crystal Ceramic and C as near as possib...

Page 47: ...gh clock source Warm up Time 2048 FAUEHS AUXTALIN AUXTALOUT Shared Pin Selection Oscillator Mode AUXTALIN pin AUXTALOUT pin GPIO GPIO AUEHS X TAL Crystal Ceramic Crystal Ceramic The resonator and the...

Page 48: ...must be provided to drive the XTALIN LXTALIN pin while the XTALOUT LXTALOUT pin should be the inverse of the input clock signal EHS X tal can have a frequency of up to 25 MHz Select this mode by sett...

Page 49: ...s selected the switch will occur when the clock source is ready Ready bits in SYS0_CSST register indicate which clock s is are ready and SYSCLKST bits in SYS0_CLKCFG register indicate which clock is c...

Page 50: ...Enable AUEHS X TAL R W 0 7 6 Reserved R 0 5 EHSFREQ Frequency range driving ability of EHS X TAL 0 12MHz 1 12MHz R W 0 4 EHSEN External high speed clock enable 0 Disable EHS X TAL 1 Enable EHS X TAL R...

Page 51: ...LKIN 25MHz 2 150MHz FVCO 330MHz 3 2 M 31 4 F 1 or 2 5 P 6 8 10 12 or 14 duty 50 2 5 6 FCLKOUT 20MHz 30MHz 40MHz 50MHz 24MHz 36MHz 48MHz 32MHz 22MHz 24MHz 50MHz with jitter 500 ps Fclkout Fclkin V V V...

Page 52: ...cillator ready R 0 1 Reserved R 0 0 IHRCRDY IHRC ready flag 0 IHRC not ready 1 IHRC ready R 1 3 3 4 System Clock Configuration register SYS0_CLKCFG Address Offset 0x0C Bit Name Description Attribute R...

Page 53: ...lag Set by HW when a reset from the RESET pin occurs 0 Read No reset from RESET pin occurred Write Clear this bit 1 Reset from RESET pin occurred R W 0 2 LVDRSTF LVD reset flag Set by HW when a LVD re...

Page 54: ...is 2 00V 01 The interrupt assertion threshold voltage is 2 40V 10 The interrupt assertion threshold voltage is 2 70V 11 The interrupt assertion threshold voltage is 3 00V R W 0 3 2 Reserved R 0 1 0 LV...

Page 55: ...1 Reserved R 0 0 RESETDIS External RESET pin disable bit 0 Enable external RESET pin P0 15 acts as RESET pin 1 Disable P0 15 acts as GPIO pin R W 0 3 3 9 SWD Pin Control register SYS0_SWDCTRL Address...

Page 56: ...ource 000 Disable 001 HCLK 010 PLL clock output 011 ILRC clock 100 IHRC clock 101 ELS clock 110 EHS clock 111 AUEHS clock R W 0 27 25 Reserved R 0 24 WDTCLKEN Enables clock for WDT 0 Disable 1 Enable...

Page 57: ...the corresponding peripheral with SYS1_PRST register after changing the prescale value Bit Name Description Attribute Reset 31 Reserved R 0 30 28 AUEHSPRE 2 0 Audio external high clock source prescal...

Page 58: ...ale value 000 HCLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved R W 0 3 4 3 APB Clock Prescale register 1 SYS1_APBCP1 Address Offset 0x08 Note Must reset the corresponding peripheral...

Page 59: ...CLK 4 011 HCLK 8 100 HCLK 16 Other Reserved R W 0 7 Reserved R 0 6 4 UART1PRE 2 0 UART1 clock source prescale value 000 HCLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved R W 0 3 Reser...

Page 60: ...o effect 1 Reset SSP0 R W 0 11 CMPRST Comparator reset 0 No effect 1 Reset Comparator R W 0 10 Reserved R 0 9 CT32B1RST CT32B1 reset 0 No effect 1 Reset CT32B1 R W 0 8 CT32B0RST CT32B0 reset 0 No effe...

Page 61: ...clock rate may also be controlled as needed by changing clock sources re configuring PLL values and or altering the system clock divider value This allows a trade off of power versus processing speed...

Page 62: ...one of GPIO port pins P0 P3 interrupt trigger or RTC interrupt The RESET pin has keep functionality in Deep sleep mode The Deep sleep mode is entered by using the following steps 1 Write 1 to DSLEEPEN...

Page 63: ...the DPDEN bit in PMU_CTRL register 4 Optional Read the stored data in the backup registers 5 Setup the PMU for the next Deep power down cycle 4 4 WAKEUP INTERRUPT System will exit Deep sleep mode when...

Page 64: ...Wakeup time 1 FEHS 2048 oscillator start up time 102 4 us oscillator start up time FEHS 20MHz The value of the IHRC wakeup time is as the following The total Wakeup time of IHRC 1 FIHRC 32 sec Exampl...

Page 65: ...sable OFF AUEHS X TAL By AUEHSEN Disable OFF ELS X TAL By ELSEN OFF PLL By PLLEN Disable OFF Cortex M0 core Running Stop Stop Stop Flash ROM Enable Disable Disable OFF RAM Enable Maintain Maintain OFF...

Page 66: ...r one of the ARM Cortex M0 controlled power down modes Sleep mode or Deep sleep mode or the Deep power down mode is entered and provides the flags for Sleep or Deep sleep modes and Deep power down mod...

Page 67: ...5 2 GPIO MODE The MODE bits in the GPIOn_CFG n 0 1 2 3 register allow the selection of on chip pull up or pull down resistors for each pin or select the repeater mode The repeater mode enables the pu...

Page 68: ...ut x 0 to 15 n 0 and x 14 is input only 0 Pn x is configured as input 1 Pn x is configured as output R W 0 Note HW will switch P1 7 and P1 8 to Microphone differential input if SEL_MIC 1 in ADC_SET23...

Page 69: ...nabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode R W 10b 15 14 CFG7 1 0 Configuration of Pn 7 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull dow...

Page 70: ...Description Attribute Reset 31 16 Reserved R 0 15 0 IBS 15 0 Selects interrupt on Pn x to be triggered on both edges x 0 to 15 0 Interrupt on Pn x is controlled through register GPIOn_IEV 1 Both edge...

Page 71: ...peration register GPIOn_BSET n 0 1 2 3 Address offset 0x24 In order for SW to set GPIO bits without affecting any other pins in a single write operation the GPIO bit is set if the corresponding bit in...

Page 72: ...y R W 0 n 0 2 Reserved R 14 Pn14OC n 3 P3 14 open drain control bit 0 Disable 1 Enable HW set P3 14 as output mode automatically R W 0 n 0 2 Reserved R 13 Pn13OC n 3 P3 13 open drain control bit 0 Dis...

Page 73: ...Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 73 Version 1 9 0 Pn0OC n 0 P0 0 open drain control bit 0 Disable 1 Enable HW set P0 0 as output mode automatically R W 0 n 1 3 Re...

Page 74: ...en an input signal transitions A capture event may also optionally generate an interrupt The timer and the prescale value may be configured to be cleared on a designated capture event This feature per...

Page 75: ...NiX TECHNOLOGY CO LTD Page 75 Version 1 9 6 4 BLOCK DIAGRAM CT16Bn_PWMx STOP MRx MRxIF MRxIE PCLK CEN PC PRE TC CEN MRx Interrupt MRxSTOP STOP CRST CRST RESET RESET MRxRST CAP0 CAP0EN CAP0FE CAP0RE CA...

Page 76: ...is reset The interrupt indicating that a match occurred is generated after the timer reached the match value PCLK CT16Bn_PC CT16Bn_TC TC Reset Interrupt 2 0 1 2 0 1 2 0 4 5 6 0 The following figure sh...

Page 77: ...as the timer reset value the PWM cycle length then the PWM output will be reset to LOW on the next clock tick Therefore the PWM output will always consist of a one clock tick wide positive pulse with...

Page 78: ...C will count up to the value 0x0000FFFF and then wrap back to the value 0x00000000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed Bit Name Desc...

Page 79: ...uently the duration of the HIGH LOW levels on the same CAP input in this case cannot be shorter than 1 2 x PCLK Note If Counter mode is selected in the CNTCTRL register Capture Control CAPCTRL registe...

Page 80: ...n Match register 0 3 CT16Bn_MR0 3 n 0 1 Address Offset 0x18 0x1C 0x20 0x24 The Match register values are continuously compared to the Timer Counter TC value When the two values are equal actions can b...

Page 81: ...R 0 15 0 CAP0 15 0 Timer counter capture value R 0 6 7 10 CT16Bn External Match register CT16Bn_EM n 0 1 Address Offset 0x30 The External Match register provides both control and status of CT16Bn_PWM...

Page 82: ...rrupt flag for capture channel 0 0 No interrupt on CAP0 1 Interrupt requirements met on CAP0 R 0 3 MR3IF Interrupt flag for match channel 3 0 No interrupt on match channel 3 1 Interrupt requirements m...

Page 83: ...when an input signal transitions A capture event may also optionally generate an interrupt The timer and the prescale value may be configured to be cleared on a designated capture event This feature...

Page 84: ...NiX TECHNOLOGY CO LTD Page 84 Version 1 9 7 4 BLOCK DIAGRAM CT32Bn_PWMx STOP MRx MRxIF MRxIE PCLK CEN PC PRE TC CEN MRx Interrupt MRxSTOP STOP CRST CRST RESET RESET MRxRST CAP0 CAP0EN CAP0FE CAP0RE CA...

Page 85: ...the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value PCLK CT32Bn_PC CT32Bn_TC TC Reset Interrupt 2 0 1 2 0 1 2 0 4 5 6...

Page 86: ...as the timer reset value the PWM cycle length then the PWM output will be reset to LOW on the next clock tick Therefore the PWM output will always consist of a one clock tick wide positive pulse with...

Page 87: ...will count up through the value 0xFFFFFFFF and then wrap back to the value 0x00000000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed Bit Name...

Page 88: ...f Counter mode is selected in the CNTCTRL register Capture Control CAPCTRL register must be programmed as 0x0 Bit Name Description Attribute Reset 31 4 Reserved R 0 3 2 CIS 1 0 Count Input Select In c...

Page 89: ...the Timer Counter or stop the timer Actions are controlled by the settings in the CT32Bn_MCTRL register Bit Name Description Attribute Reset 31 0 MR 31 0 Timer counter match value R W 0 7 7 8 CT32Bn C...

Page 90: ...0 Determines the functionality of CT32Bn_PWM1 00 Do Nothing 01 CT32Bn_PWM1 pin is LOW 10 CT32Bn_PWM1 pin is HIGH 11 Toggle CT32Bn_PWM1 R W 0 5 4 EMC0 1 0 Determines the functionality of CT32Bn_PWM0 0...

Page 91: ...is set Bit Name Description Attribute Reset 31 5 Reserved R 0 4 CAP0IF Interrupt flag for capture channel 0 0 No interrupt on CAP0 1 Interrupt requirements met on CAP0 R 0 3 MR3IF Interrupt flag for...

Page 92: ...atchdog and setup the Watchdog timer operating mode in WDT_CFG register 5 The Watchdog should be fed again by writing 0x55AA to WDT_FEED register before the Watchdog counter underflows to prevent rese...

Page 93: ...ro Controller SONiX TECHNOLOGY CO LTD Page 93 Version 1 9 8 2 BLOCK DIAGRAM WDT_FEED WDT_TC 128 8 bit Down Counter WDINT WDTIE WDTEN WDT_PCLK Feed OK Feed Watchdog Enable Counter Reload Counter underf...

Page 94: ...will reset the MCU and will clear the WDINT flag 1 Watchdog timeout will cause an interrupt Watchdog interrupt mode R W 0 0 WDTEN Watchdog enable 0 Disable 1 Enable When enable the watchdog the WDT_TC...

Page 95: ...r constant 255 1111 1111 Timer constant 256 R W 0xFF 8 3 4 Watchdog Feed register WDT_FEED Address Offset 0x0C Bit Name Description Attribute Reset 31 16 WDKEY Watchdog register key Read as 0 When wri...

Page 96: ...o detect when the internal programmable counter rolls over to zero 9 3 FUNCTIONAL DESCRIPTION 9 3 1 INTRODUCTION RTC core includes a 20 bit preload value RTC SECCNTV Every TR_CLK period the RTC genera...

Page 97: ...s configured with RTC_SECCNTV 3 RTC_ALMCNTV 0x1000 RTC_PCLK 0x0 Cleared by SW r RTC_SECCNT 0x1 0x2 0x3 RTC_SECIF 0x0 0x1 0x2 0x3 0x0 0x0 RTC_ALMCNT 0x1 0x2 0x0 0x1 0x2 0x3 0x0 0x9FF 0x1000 0x3 0x1001...

Page 98: ...TECHNOLOGY CO LTD Page 98 Version 1 9 9 4 BLOCK DIAGRAM RTC_SECCNT RTC_ALMCNT SRC_SEL ELS_XTAL EHS_XTAL 128 ILRC SEC_CNT_CLK RTC_SECCNTV RTC_ALMCNTV SECOND SECIF ALMIF OVFIF RTCEN SECIE SECOND Interru...

Page 99: ...k source selection HW will reset SEC_CNT and ALM_CNT when changing the value 00 ILRC 01 ELS X TAL 10 Reserved 11 EHS X TAL clock 128 R W 0 9 5 3 RTC Interrupt Enable register RTC_IE Address offset 0x0...

Page 100: ...s offset 0x14 Reset value 0x8000 Bit Name Description Attribute Reset 31 20 Reserved R 0 19 0 SECCNTV 19 0 RTC second counter reload value Update this register will reset RTC_SECCNT and RTC_ALMCNT reg...

Page 101: ...Controller SONiX TECHNOLOGY CO LTD Page 101 Version 1 9 9 5 9 RTC Alarm Count register RTC_ALMCNT Address offset 0x20 Bit Name Description Attribute Reset 31 0 ALMCNT 31 0 RTC alarm counter The curren...

Page 102: ...with frames of 4 to 16 bits of data flowing from the master to the slave and from the slave to the master In practice it is often the case that only one of these data flows carries meaningful data 10...

Page 103: ...nfiguration SCKn O SSP Serial clock Master I SSP Serial clock Slave Depends on GPIOn_CFG SELn O SPI Slave Select SSI Frame Sync Master I SSP Slave Select Slave Depends on GPIOn_CFG MISOn I Master In S...

Page 104: ...control bit is HIGH a steady state high value is placed on the CLK pin when data is not being transferred The CPHA clock phase bit controls the phase of the clock on which data is sampled When CPHA 1...

Page 105: ...the serial shift register of the shifted out on the DATA pin Likewise the MSB of the received data is shifted onto the DATA pin by the off chip serial slave device Both the SSP hardware and the off c...

Page 106: ...to SEL function is enabled by default and Auto SEL data flow is controlled by hardware If Auto SEL function is enabled the SPI s hardware controls the SEL output of the SPI If Auto SEL function is dis...

Page 107: ...vel 0 1 RX FIFO threshold level 1 n RX FIFO threshold level n R W 000b 14 12 TXFIFOTH 2 0 TX FIFO Threshold level 0 TX FIFO threshold level 0 1 TX FIFO threshold level 1 n TX FIFO threshold level n R...

Page 108: ...0 6 3 SSP n Clock Divider register SSPn_CLKDIV n 0 1 Address Offset 0x08 Bit Name Description Attribute Reset 31 8 Reserved R 0 7 0 DIV 7 0 SSPn clock divider 0 SCK SSPn_PCLK 2 1 SCK SSPn_PCLK 4 2 SCK...

Page 109: ...pt is sent to the interrupt controller if the corresponding bit in the SSPn_IE register is set Bit Name Description Attribute Reset 31 4 Reserved R 0 3 TXFIFOTHIF TX FIFO threshold interrupt flag 0 No...

Page 110: ...t busy on the bus transmission of the data will begin immediately Otherwise the data written to this register will be sent as soon as all previous data has been sent and received Read SW can read data...

Page 111: ...eived bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A t...

Page 112: ...diagnostic purposes Generation and detection of 7 bit 10 bit addressing and General Call 11 3 PIN DESCRIPTION Pin Name Type Description GPIO Configuration SCLn I O I2C Serial clock Output with Open d...

Page 113: ...4 D4 5 D3 6 D2 7 D1 P 9 D6 ACK_ 9 8 D0 D0 Write 1 to ACK bit Start Acknowledge sequence ACK from Master Receiving Data from Slave ACK_ is not sent Write 1 to STO bit Master terminal transfer Data shif...

Page 114: ...7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R W 0 ACK_ 1 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 9 P SDA SCL Transmission Data R W 1 D7 11 6 2 SLAVE RECEIVER MODE S Receiving Address ACK_ 1 A7 2 A6 3 A5 4 A4 5 A3...

Page 115: ...ve on the bus which was actually addressed by the master Following all of these interrupts the processor may read the data register to see what was actually transmitted on the bus 11 7 2 LOSS of ARBIT...

Page 116: ...ion thereafter If the I2C interface is in slave mode an internal STOP condition is generated but is not transmitted on the bus Note 1 I2CEN shall be set at last 2 HW will assign SCL0 SCL1 and SDA0 SDA...

Page 117: ...r I2C interrupt if I2C interrupt is enabled in NVIC interrupt controller START Repeat START condition STOP condition Timeout Data byte transmitted or received ACK Transmit or received NACK Transmit or...

Page 118: ...Address 0 register I2Cn_SLVADDR0 n 0 1 Address Offset 0x10 Only used in slave mode In master mode this register has no effect If this register contains 0x00 the I2C will not acknowledge any address o...

Page 119: ...N Timeout period time N 32 I2Cn_PCLK cycle R W 0x0 11 8 10 I2C n Monitor Mode Control register I2Cn_MMCTRL n 0 1 Address Offset 0x30 This register controls the Monitor mode which allows the I2C module...

Page 120: ...SN32F100 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 120 Version 1 9 interrupt 0 MMEN Monitor mode enable bit 0 Disable 1 Enable R W 0...

Page 121: ...r and communicate with low speed peripheral devices The UART offers a very wide range of baud rates using a fractional baud rate generator 12 2 FEATURES Full duplex 2 wire asynchronous data transfer S...

Page 122: ...tex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 122 Version 1 9 12 4 BLOCK DIAGRAM UART Baud Rate Generator RX DLL DLM UARTn_RB RSR TX UARTn_TH TSR UTXD URXD APB SCR INTERRUPT UARTn_IE UARTn_II U...

Page 123: ...AL MULVAL 4 Oversampling is 8 or 16 The value of the UARTn_FD register should not be modified while transmitting receiving data or data may be lost or corrupted The oversampling method can be selected...

Page 124: ...the bit time of the receive data stream and set the divisor latch registers UARTn_DLM and UARTn_DLL accordingly Auto baud function is started by setting the START bit in UARTn_ABCTRL register and can...

Page 125: ...e is switched to the highest rate 2 A falling edge on URXD pin triggers the beginning of the start bit The rate measuring counter will start counting UARTn_PCLK cycles 3 During the receipt of the star...

Page 126: ...0 Micro Controller SONiX TECHNOLOGY CO LTD Page 126 Version 1 9 bit1 bit3 bit4 bit5 bit6 Start bit7 Parity Stop URXD bit0 bit2 A 0x41 or a 0x61 Start bit LSB of A or a Rate Counter 16 Cycles 16 x Baud...

Page 127: ...IFO and can be written via the bus interface The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in UARTn_LC register must be zero in order to access this register Bit Name...

Page 128: ...able 1 Enable R W 0 0 RDAIE RDA interrupt enable bit Enables the Receive Data Available interrupt It also controls the Character Receive Time out interrupt 0 Disable 1 Enable R W 0 12 7 6 UART n Inter...

Page 129: ...he cause of the interrupt and how to clear the active interrupt The UARTn_II register must be read in order to clear the interrupt prior to exiting the Interrupt service routine Interrupt UARTn_II 3 0...

Page 130: ...FOCTRL 7 1 access This bit must be set for proper UART operation W 1 12 7 8 UART n Line Control register UARTn_LC n 0 1 Address Offset 0x0C This register determines the format of the data character th...

Page 131: ...character transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXD1 goes to marking state all ones A UARTn_LS register r...

Page 132: ...lear bit 0 No effect 1 Clear ABTOIF bit This bit is automatically cleared by HW W 0 8 ABEOIFC End of auto baud interrupt flag clear bit 0 No effect 1 Clear ABEOIF bit This bit is automatically cleared...

Page 133: ...the receiver Bit Name Description Attribute Reset 31 8 Reserved R 0 7 TXEN When this bit is 1 data written to the UARTn_TH register is output on the TXD pin as soon as any preceding data has been sent...

Page 134: ...100 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 134 Version 1 9 Bit Name Description Attribute Reset 31 1 Reserved R 0 0 HDEN Half duplex mode enable bit 0 Disable 1 Enable R...

Page 135: ...s Audio Gain Controller AGC is programmable to monitor the input and further adjust the volume properly The DAC includes a power supply input for DAC driver a power supply input pins for DAC a DAC VMI...

Page 136: ...escription GPIO Configuration AVDD_ADC AVSS_ADC P Power supply input pins for Sigma delta ADC VMID_ADC P Sigma delta ADC VMID output MIC_BIAS P Sigma delta ADC Microphone Bias Voltage output MIC_P I O...

Page 137: ...4 1 I2S CLCOK CONTROL I2S_PCLK HCLK MCLK_I MCLK_ SOURCE MCLKDIV MCLK MCLKO_EN MCLK_O MCLK_SEL BCLKDIV BCLK_O BCLK_I MS BCLK BCLK_O I2S DIV I2S_MCLK 13 4 2 I2S BLOCK DIAGRAM I2S CLOCK CONTROL 8 x 32 bi...

Page 138: ...SN32F100 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 138 Version 1 9 13 4 3 16 Bit Sigma Delta ADC BLOCK DIAGRAM...

Page 139: ...SN32F100 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 139 Version 1 9 13 4 4 16 Bit Sigma Delta DAC BLOCK DIAGRAM...

Page 140: ...SB Left justified Data Format Channel Length Data Length msb BCLK SD WS lsb 0 0 0 msb lsb 0 0 0 msb Channel length Left Channel length Right Data length I2S msb BCLK SD WS lsb 0 0 0 msb lsb 0 0 0 msb...

Page 141: ...rtex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 141 Version 1 9 Channel Length Data Length msb BCLK SD WS lsb msb lsb msb I2S msb BCLK SD WS lsb msb lsb msb Left Justified msb BCLK SD WS lsb msb...

Page 142: ...42 Version 1 9 13 5 2 I2S FIFO OPERAION 13 5 2 1 MONO 8bit N 3 N 2 N 1 N N 7 N 6 N 5 N 4 16bit N 1 N N 3 N 2 24 bit N N 1 32 bit N N 1 13 5 2 2 STEREO 8bit RIGHT 1 LEFT 1 RIGHT LEFT RIGHT 3 LEFT 3 RIG...

Page 143: ...0 1 0 6 Reserved 7 8 bits 8 9 bits 31 32bits Max If I2SEN 1 and I2SMOD 1 HW will switch channel length 32bits R W 0x1F 19 Reserved R 0 18 16 RXFIFOTH 2 0 RX FIFO Threshold level 0 RX FIFO threshold le...

Page 144: ...START Start Transmit Receive bit 0 Stop Transmit Receive 1 Start Transmit Receive R W 0 13 6 2 I2S Clock register I2S_CLK Address Offset 0x04 Bit Name Description Attribute Reset 31 16 Reserved R 0 15...

Page 145: ...FIFO is not full 1 TX FIFO is full Write operation to TX FIFO will be ignored R 0 7 RXFIFOTHF RX FIFO threshold flag 0 RXFIFOLV RXFIFOTH 1 RXFIFOLV RXFIFOTH R 0 6 TXFIFOTHF TX FIFO threshold flag 0 TX...

Page 146: ...R 0 13 6 6 I2S Interrupt Clear register I2S_IC Address Offset 0x14 Bit Name Description Attribute Reset 31 8 Reserved R 0 7 RXFIFOTHIC 0 No effect 1 Clear RXFIFOTHIF bit W 0 6 TXFIFOTHIC 0 No effect 1...

Page 147: ...Offset 0x570 Bit Name Description Attribute Reset 31 8 Reserved R 0 7 0 HB_L AGC Control High bound setting for output amplitude of ADC Low byte R W 0x00 13 7 5 ADC Setting 5 register ADC_SET5 Addres...

Page 148: ...etting are equal to the setting in ADC_SET19 Then the internal digital gain is adjusted to default value Finally the AGC is entering mute mode until the ADC output is over search threshold in ADC_SET7...

Page 149: ...ved R 0 7 AGC_OFF AGC Control AGC function 0 Enable 1 Disable R W 0x01 6 5 BOOST_SET_VAL AGC Control Boost setting value at normal mode when AGC is on 00 0dB 01 12dB 10 20dB 11 30dB R W 0x03 4 0 PGA_S...

Page 150: ...B 0111 21dB 1000 24dB 1001 27dB 1010 30dB 1011 36dB 1100 42dB 1101 48dB 1110 54dB 1111 78dB R W 0x00 3 0 MUTE_CTRL Digital Volume attenuation control At the mute mode when AGC is on 0000 0dB 0001 3dB...

Page 151: ...escription Attribute Reset 31 8 Reserved R 0 7 ADC_EN ADC power on enable active High R W 0 6 Reserved R 0 5 MICBT_EN MICBOOST power on enable active High R W 0 4 PGA_EN PGA power on enable active Hig...

Page 152: ..._CLK CKGEN Power down active High R W 1 5 PD_IREF IREF Circuit Power down active High R W 1 4 3 Reserved R 0 2 PD_VREF VREF Circuit Power down active High R W 1 1 VMIDSEL Normal mode Fast Start up sel...

Page 153: ...e emphasis for 48 kHz 2 De emphasis for 44 1 kHz 3 De emphasis for 32 kHz R W 0 0 INI_RAM_EN Initialize DAC RAM Set 1 until Ini_RAM_Ready 1 then clear this bit R W 0 13 8 5 DAC Status register DAC_STA...

Page 154: ...ntrol Flow 13 10 1Sigma delta DAC Power up Sequence Step1 PD_IREF 0 Step2 VMIDSEL 1 Step3 PD_VREF 0 Step4 VMIDSEL 0 Step5 PD_DAC 0 Step6 PD_CLK 0 Step7 After PD_CLK delay 6 3us Step8 After I2S data re...

Page 155: ...ndicator function The comparator has flag indicator interrupt function and sleep mode weak up function for different application 24 channel negative input selection Comparator output function Programm...

Page 156: ...m will be wake up from sleep mode If the trigger edge direction is interrupt trigger condition the CMPIRQ is set as 1 Of course the interrupt routine is executed if the interrupt function enabled When...

Page 157: ...or output terminal connects to internal path The CMPOUT flag is the CMPOUT shows the comparator result immediately but the CMPIRQ only indicates the event of the comparator result The comparator outpu...

Page 158: ...reference voltage generator R W 0 4 0 CMCH 4 0 Comparator negative input pin control bit CMPEN must be 1 00000 Comparator negative input pin is P2 0 00001 Comparator negative input pin is P2 1 00010 C...

Page 159: ...ates the status for Comparator control raw interrupts A Comparator interrupt is sent to the interrupt controller if the corresponding bit in the CMP_IE register is set Bit Name Description Attribute R...

Page 160: ...and is located at a specific base address in the memory map of chip The high performance Flash memory module in chip has the following key features Memory organization the Flash memory is organized a...

Page 161: ...module through dedicated read senses and provides the requested data The read interface consists of a read controller on one side to access the Flash memory and an AHB interface on the other side to...

Page 162: ...e only after the MCU has been Reboot User ROM CS0 CS1 CS2 CS3 Description WRITER Read O X X X Erase O O O O WRITER will change the CS level to CS0 Program O O O O FW EEPROM emulation Read O O O O Eras...

Page 163: ...r the BUSY bit to be reset Read the programmed value and verify 15 8 3 ERASE The Flash memory can be erased page by page or completely Mass Erase 15 8 3 1 PAGE ERASE A page of the Flash memory can be...

Page 164: ...This is set on the beginning of a Flash operation clear EOP bit at the same time and reset when the operation finishes or when an error occurs by HW R 0 15 10 2Flash Control register FLASH_CTRL Addre...

Page 165: ...r programmed should be updated by SW and the PG bit or PER bit shall be set before filling in the Flash address Note Write access to this register is blocked when the BUSY bit in the FLASH_STATUS regi...

Page 166: ...power modes work internal to the ARM Cortex M0 CPU and this ripples through the entire system These differences mean that power measurements should not be made while debugging the results will be high...

Page 167: ...PULL UP DOWN RESISTORS on SWD PINS To avoid any uncontrolled IO levels the device embeds internal pull up and pull down resistor on the SWD input pins NJTRST Internal pull up SWDIO JTMS Internal pull...

Page 168: ...SN LINK V2 USB cable to provide communications between the SN LINK V2 and PC IDE Tools KEIL RVMDK SN32F100 Starter Kit SN LINK V2 IDE Tools SONiX 32 bit series Embedded ICE Emulator Feature Target s O...

Page 169: ...bit MCU It debugs and programs based on SWD protocol In addition to debugger functions the SN LINK V2 also may be used as a programmer to load firmware from PC to MCU for engineering production even...

Page 170: ...sy development platform It includes SN32F109 real chip and I O connectors to input signal or drive extra device of user s application It is a simple platform to develop application as target board not...

Page 171: ...l Y2 External low speed 32 768KHz X tal Y3 External high speed X tal for Audio JP18 SN LINK connector JP15 Writer connector JP20 Short to force MCU stay in Boot loader JP21 I2S connector JP3 JP4 I2C0...

Page 172: ...Mini USB connector for power supply S1 USB power on off JP53 VDD power source is 3 3V from board Writer or external power Open if External power source is used U4 SN32F109F real chip D9 Power LED RES...

Page 173: ...PI1 connector JP8 JP9 UART0 UART1 connector R1 SCL0 pull up resistor R3 SDA0 pull up resistor R2 SCL1 pull up resistor R4 SDA1 pull up resistor R5 UTXD0 pull up resistor R6 URXD0 pull up resistor R41...

Page 174: ...Idd1 Normal mode System clock 12MHz 1 3 4 7 8 2 mA System clock 50MHz 1 3 5 20 30 2 mA Idd2 Sleep Mode System clock 12MHz 1 3 4 7 2 4 2 65 2 mA System clock 16KHz 1 3 6 7 500 700 2 uA Idd3 Deep sleep...

Page 175: ...V VSS 0V 1KHz input RL 16 Po 20mW 6dBr 75 dB FLASH Supply Voltage Vdd1 1 8 Vdd V Endurance time TEN Erase Program 20K 100K Cycle Page erase time TPE 1 Page 1024 bytes 25 30 ms 1 Word Programming time...

Page 176: ...n 1 9 18 3 CHARACTERISTIC GRAPHS The Graphs in this section are for design guidance not tested or guaranteed In some graphs the data presented are outside specified operating range This is for informa...

Page 177: ...ortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 177 Version 1 9 Supply Current V S Operating Temperature Operating Conditions All pins configured as GPIO outputs driven Low and pull up resistor...

Page 178: ...Writer Connector Flash IC JP3 Pin Assignment Number Name Number Pin Number Pin Number Pin Number Pin Number Pin 1 VDD 41 61 80 VDD 32 49 64 VDD 27 48 VDD 2 GND 42 62 79 VSS 33 50 63 VSS 28 47 VSS 3 P...

Page 179: ...ONiX TECHNOLOGY CO LTD Page 179 Version 1 9 2 2 20 0 0 PACKAGE INFORMATION 20 1 LQFP 48 PIN SYMBOLS MIN NOR MAX mm A 1 6 A1 0 05 0 15 A2 1 35 1 45 c1 0 09 0 16 D 9 00 BSC D1 7 00 BSC E 9 00 BSC E1 7 0...

Page 180: ...SN32F100 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 180 Version 1 9 20 2 LQFP 64 PIN...

Page 181: ...SN32F100 Series 32 Bit Cortex M0 Micro Controller SONiX TECHNOLOGY CO LTD Page 181 Version 1 9 20 3 LQFP 80 PIN...

Page 182: ...MCU production line This note lists the marking definitions of all 32 bit MCU for order or obtaining information 21 2 MARKING INDETIFICATION SYSTEM Title SONiX 32 bit MCU Production ROM Type F Flash m...

Page 183: ...FP 40 85 Green Package SN32F109W Flash memory 109 Wafer 40 85 SN32F109H Flash memory 109 Dice 40 85 SN32F108FG Flash memory 109 LQFP 40 85 Green Package SN32F107FG Flash memory 109 LQFP 40 85 Green Pa...

Page 184: ...hould Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors...

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