SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 50
Version 1.9
3.3 SYSTEM CONTROL REGISTERS 0
Base Address: 0x4006 0000
3.3.1 Analog Block Control register (SYS0_ANBCTRL)
Address Offset: 0x00
Reset value: 0x0000 0001
Note: EHSEN / ELSEN / IHRCEN bit can NOT be cleared if the EHS X’tal / ELS X’tal / IHRC is selected as
system clock or is selected to become the system clock.
Bit
Name
Description
Attribute
Reset
31:10
Reserved
R
0
9
AUEHSFREQ
Frequency range of AUEHS X’TAL
0: <=12MHz
1: >12MHz
R/W
0
8
AUEHSEN
Audio external high-speed clock enable
0: Disable AUEHS X’TAL.
1: Enable AUEHS X’TAL.
R/W
0
7:6
Reserved
R
0
5
EHSFREQ
Frequency range (driving ability)
of EHS X’TAL
0: <=12MHz
1: >12MHz
R/W
0
4
EHSEN
External high-speed clock enable
0: Disable EHS X’TAL.
1: Enable
EHS X’TAL.
R/W
0
3
Reserved
R
0
2
ELSEN
External low-speed oscillator enable
0: Disable External 32.768 KHz oscillator
1: Enable External 32.768 KHz oscillator
R/W
0
1
Reserved
R
0
0
IHRCEN
Internal high-speed clock enable
0: Disable internal 12 MHz RC oscillator.
1: Enable internal 12 MHz RC oscillator.
R/W
1
3.3.2 PLL control register (SYS0_PLLCTRL)
Address Offset: 0x04
Note: PLLEN bit can NOT be cleared if the PLL is selected as system clock or is selected to become the
system clock.
Bit
Name
Description
Attribute
Reset
31:16
Reserved
R
0
15
PLLEN
PLL enable
0: Disable
1: Enable
R/W
0
14
Reserved
R
0
