SONIX SN32F107, User Manual

Page: 109 / 184

SN32F100 Series
32-Bit Cortex-M0 Micro-Controller
SONiX TECHNOLOGY CO., LTD
Page 109
Version 1.9
10.6.5 SSP n Interrupt Enable register (SSPn_IE) (n=0, 1)
Address Offset: 0x10
This register controls whether each of the four possible interrupt conditions in the SSP controller is enabled.
Bit Name Description Attribute Reset
31:4 Reserved R 0
3 TXFIFOTHIE
TX FIFO threshold interrupt enable
0: Disable
1: Enable
R/W 0
2 RXFIFOTHIE
RX FIFO threshold interrupt enable
0: Disable
1: Enable
R/W 0
1 RXTOIE
RX time-out interrupt enable
0: Disable
1: Enable
R/W 0
0 RXOVFIE
RX Overflow interrupt enable
0: Disable
1: Enable
R/W 0
10.6.6 SSP n Raw Interrupt Status register (SSPn_RIS) (n=0, 1)
Address Offset: 0x14
This register contains the status for each interrupt condition, regardless of whether or not the interrupt is enabled in
SSPn_IE register.
This register indicates the status for SSP control raw interrupts. An SSP interrupt is sent to the interrupt controller if the
corresponding bit in the SSPn_IE register is set.
Bit Name Description Attribute Reset
31:4
Reserved R 0
3 TXFIFOTHIF
TX FIFO threshold interrupt flag
0: No TX FIFO threshold interrupt
1: TX FIFO threshold triggered.
R 0
2 RXFIFOTHIF
RX FIFO threshold interrupt flag
0: No RX FIFO threshold interrupt
1: RX FIFO threshold triggered.
R 0
1 RXTOIF
RX time-out interrupt flag
RXTO occurs when the RX FIFO is not empty, and has not been read for a
time-out period (32*SSPn_PCLK). The time-out period is the same for
master and slave modes.
0: RXTO doesn’t occur.
1: RXTO occurs.
R 0
0 RXOVFIF
RX Overflow interrupt flag
RXOVF occurs when the RX FIFO is full and another frame is completely
received. The ARM spec implies that the preceding frame data is
overwritten by the new frame data when this occurs.
0: RXOVF doesn’t occur.
1: RXOVF occurs.
R 0
10.6.7 SSP n Interrupt Clear register (SSPn_IC) (n=0, 1)
Address Offset: 0x18
Bit Name Description Attribute Reset
31:4 Reserved R 0
3 TXFIFOTHIC
0: No effect
1: Clear TXFIFOTHIF bit.
W 0
2 RXFIFOTHIC
0: No effect
1: Clear RXFIFOTHIF bit.
W 0