SMART Embedded Computing MC1600, Installation And Use Manual

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56 MC1600 Extreme Edge Server Installation and Use (6806870A02B)
System Overview
System Overview
On the Extreme Edge Server, the x8 port (PE2) of each CPU is bifurcated into two x4 ports.
These ports connect to the M.2 NVMe modules according to the following table.
1.7.1.2 PCI Express Gen2
The Integrated PCH Logic additionally implements eight lanes of PCIe Gen2 that can be
split into eight root ports. The ports support Gen1 (2.5Gb/s) and Gen2 (5Gb/s) speeds.
Lanes 1-4 and lanes 5-8 can independently be configured as four x1, two x2, one x2 and
two x1, or one x4 port(s).
On the Extreme Edge Server, lanes 1-4 of CPU1 and CPU2 are configured as four x1 ports.
These ports are connected according to the following table. Default routing of the second
MAC/PHY is to CPU2 on dual-CPU variants, and to CPU1 on single-CPU variants.
Table 1-4 PCI Express Gen3 Interfaces to PCIe Connector
CPU
IIO
Port IIO Port
Lanes Bifurcated
Port Bifurcated
Port Lanes Destination
(PCIe Connector Signals)
CPU1 PE1 <7:0> 1 <7:0> PETp/PETn<7:0> and PERp/PERn <7:0>
CPU2 PE1 <7:0> 1 <7:0>
PETp/PETn<15:8> and PERp/PERn
<15:8>
Table 1-5 PCI Express Gen3 Interfaces to M.2 Modules
CPU IIO Port
IIO Port
Lanes Bifurcated
Port Bifurcated Port
Lanes
Destination
CPU1 PE2 <3:0> 1 <3:0> M.2 (Primary)
CPU1 PE2 <7:4> 2 <3:0> M.2 (Secondary)
CPU2 PE2 <3:0> 1 <3:0> M.2
Table 1-6 PCI Express Gen2 (PCH) Interfaces
CPU
PCH PCIe
Port Group
Port (Lane) Destination Link Speed
CPU1 Lanes 1-4 1 Ethernet Switch 5.0Gbps (Gen2)
CPU1 Lanes 1-4 2 Ethernet MAC/PHY A 2.5Gbps (Gen1)
CPU1 Lanes 1-4 3 Ethernet MAC/PHY B (option) 2.5Gbps (Gen1)
CPU2 Lanes 1-4 3 Ethernet MAC/PHY B (default) 2.5Gbps (Gen1)
CPU1 Lanes 1-4 4 BMC 2.5Gbps (Gen1)