Schweitzer Engineering Laboratories SEL-352-1, Instruction Manual

Page: 79 / 444

Date Code 20010731 Breaker Logic 3-7
SEL-352-1, -2 Instruction Manual
magnitude of the half-cosine filtered IA to equal the value for |IhA|. The overcurrent element
50FTA compares |IhA| to the pickup setting 50FT. If |IhA| is greater than 50FT, the element is
picked up and Relay Word bit 50FTA asserts; if |IhA| is less than 50FT, the element is dropped
out and 50FTA deasserts.
When the primary ac current is interrupted, the CT secondary current IA in the upper drawing
can take on a decaying dc exponential form, the subsidence current. Here, the zero-crossing
detectors are likely to see few or no crossings. The output of the AND gate will now persist
longer than the 5/8-cycle timer pickup value, so setting OPHA = 1. In the lower drawing, with
OPHA = 1, the “switch” causes |IhA| to be set to zero, rather than to the calculated magnitude of
IA. This setting of |IhA| to zero causes immediate dropout of the 50FTA element. Had |IhA|
remained equal to |IA|, the detection of dropout may have been delayed considerably. Thus, the
subsidence current detection logic, by sensing the presence of the exponential dc current, forces
the overcurrent element to drop out sooner and permits faster breaker failure timing margins.
While the subsidence current detection logic operates nominally in about 5/8 cycle, processing
latency could, in the worst case, stretch the 50FT dropout time to 3/4 cycle.
Scheme 1 (Fault Current)
Consider reading about Scheme 5 and then Scheme 4 before Scheme 1. These schemes are
easier to understand than Scheme 1.
Scheme 1 (FTLOG=1) provides breaker failure protection for breaker-and-a-half and ring-bus
breaker applications; it also can be used for single-breaker applications. This scheme adds a
set/reset latch, a rising edge latch and dropout timer, and other logic to the logic of Scheme 5 to
allow for a pulsed trip input. The 62TT timer latches the trip input for time TTdo when the input
is asserted for a quarter-cycle. The 62FC breaker failure timer resets when both the 62TT timer
dropout time (TTdo) expires and the 50FT element drops out. This timing scheme provides
consistent breaker failure clearing times between adjacent breakers. This logic is necessary in
multiple breaker applications because the fault current may be below the fault current threshold
for one breaker until the adjacent breaker clears.
To understand the operation of the Scheme 1 logic, review two possible scenarios:
1) The 50FTA element asserts before the TRIPA input asserts.
2) The TRIPA input asserts before the 50FTA element asserts.
----------------
1) If the 50FTA element picks up before TRIPA assertion, the 62FC timer starts when the
TRIPA input asserts. The 62FC timer continues to time until 50FTA drops out and the
62TT timer expires. If the 62FC timer expires, the FBF bit in the Relay Word asserts.
2) In ring-bus and breaker-and-a-half installations, the TRIPA input can assert before the
50FT overcurrent element picks up. If the TRIPA input asserts before the 50FT element
picks up, the 62TT timer output asserts and the 62FC timer starts. The 62TT timer
output remains asserted for TTdo time. The 62FC timer continues to time until the 62TT
timer has expired and the 50FTA overcurrent element drops out. If the 50FTA element
picks up and remains asserted until 62FC expires, the FBF bit in the Relay Word asserts.