11-32
Testing and Troubleshooting
Date Code 20010731
SEL-352-1, -2 Instruction Manual
repetition, apply phase current below the 50LD setting with at least one of the
inputs asserted. In these repetitions, the relay should not assert the UBBF bit.
8. This step is optional. To test logic operation under conditions that could represent
normal relay/breaker operation, repeat Steps 3 and 4. This time, turn on C-phase
current 1.5 to 2.0 cycles before the UFpu timer expires. The UBBF bit should not
assert.
9. Repeat Steps 3, 4, 5, 6, 7, and 8 (optional) for B-phase and C-phase, the phase
under test being the phase with no current applied in Step 4.
10. In Step 5, UPpu timer expiration can cause the relay to generate an event report.
You can set the UBPF bit in a programmable output contact and perform Steps 3,
4, 5, 6, 7, and 8 for the current unbalance pending failure logic.
11. For each test, the relay generated a sequential events record for the elements
programmed in Step 1. View the SER using the
SER
command. These time
stamps will also verify the UCpu, UFpu, and UPpu timers. The UFpu and UPpu
times are the times between the assertion of 46A and the assertion of UBBF and
UBPF, respectively. If current is applied before the CLOSE or MCLOSE input,
the UCpu time is the time between the assertion of the input and the assertion of
UBBF with the UFpu time subtracted out.
L
OSS
-
OF
-D
IELECTRIC
L
OGIC
T
EST
Purpose: Verify the loss-of-dielectric logic (Reference: Figure 3.26).
Method: 1. Using
the
SET
command, set one output to close when the LODBF element
asserts and another output to close when LODPF element asserts, and set the SER
to trigger for the listed elements. Verify the settings with the
SHO
and
SHO G
commands.
Setting
Elements
L2pu, LOD1,
LOD2, LODCT
LODBF, LODPF, LOD1, LOD2, LODCT
2. Connect a timer to start when dc control voltage is applied to the LOD1 input and
stop when the output contact programmed for LODBF closes.
3. Assert the LOD1 input by applying dc control voltage to the assigned input
terminals. Verify that the output contact programmed for LODBF in Step 1
closes.
4. Record the time from Step 3. This time should be close to one second.
5. Reconnect the timer to start when dc control voltage is applied to the LOD2 input
and stop when the output contact programmed for LODPF closes.
6. Assert the LOD2 input by applying dc control voltage to the assigned input
terminals. Verify that the output contact programmed for LODPF in Step 1
closes.
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