Date Code 20010731
Testing and Troubleshooting
11-31
SEL-352-1, -2 Instruction Manual
8. Repeat Steps 3, 4, 5, 6, and 7 for B-phase and C-phase.
9. In Step 5, 62FP timer expiration can cause the relay to generate an event report.
You can set the FOPF bit in a programmable output contact equation and perform
Steps 3, 4, 5, 6, and 7 for the flashover pending failure logic.
10. For each test, the relay generated a sequential events record for the elements
programmed in Step 1. View the SER using the
SER
command. These time
stamps will also verify the FFpu and FPpu timers. The FFpu and FPpu times are
the times between the assertion of 50LD and the assertion of FOBF and FOPF,
respectively.
Note:
Because this test involves simultaneous application of voltage and current to the
relay, the breaker resistor thermal protection elements can acquire energy. To
reset resistor thermal model energies to zero, type
HEA R <ENTER>
after each
phase test.
C
URRENT
U
NBALANCE
, F
AILURE
T
O
C
LOSE
L
OGIC
T
EST
Purpose: Verify operation of the current unbalance logic (Reference: Figure 3.23).
Method: 1. Using
the
SET
command, set an output to close when the UBBF element asserts,
and set the SER to trigger for the elements listed below. Verify the settings with
the
SHO
command, and the
SHO G
command for MCLOSE and CLOSE. Note
that UBLOG must be set to ON.
Setting
Elements
UBLOG, UCpu,
UFpu, UPpu,
50LD, 46UB,
MCLOSE,
CLOSE
50LD, 46A, FOBF, FOPF, MCLOSE, CLOSE
2. Connect an external timer, and set it to start when you apply B- or C-phase current
and stop when the programmable output you set in Step 1 asserts.
3. Assert the CLOSE and/or the MCLOSE input(s) by applying rated control voltage
to the input terminals.
4. Apply B- and C-phase current above the 50LD setting. This action should start
the external timer.
5. Shortly after you apply phase current, the programmable output contact set in Step
1 should close, indicating UBBF bit assertion. This action should stop the
external timer. Record the timer reading. It should be close to the UFpu timer
setting.
6. Shut off phase current.
7. Repeat Steps 3, 4, and 6 three times. During the first two repetitions, do not assert
the CLOSE or MCLOSE inputs before applying phase current. During the second
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