Schweitzer Engineering Laboratories SEL-352-1, Instruction Manual

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Date Code 20010731 Installation 2-21
SEL-352-1, -2 Instruction Manual
EIA-232 Serial Port Jumpers
Refer to Figure 2.16. Jumpers JMP1 and JMP2 are toward the rear of the main board, near the
rear-panel EIA-232 serial communications ports. These jumpers connect or disc5 Vdc
to Pin 1 on the EIA-232 serial communications Ports 2 and 3. SEL normally ships relays with
these jumpers removed (out of place) so that the +5 Vdc is not connected to Pin 1 on the
EIA-232 serial communications ports. JMP1 controls the +5 Vdc for Port 3, and JMP2 controls
the +5 Vdc for Port 2 (see Table 8.1 in
Section 8: Serial Port Communications and
Commands ). If these jumpers are installed, be certain not to short the power supply with an
incorrect communication cable. The +5 Vdc connections supply current as high as 1 A.
Solder jumpers JMP3 and JMP4 allow connection of an IRIG-B source to Port 2. Removal of
JMP3 and JMP4 will cause Port 2 to no longer accept an IRIG-B signal. The Port 1 connector
always accepts an IRIG-B signal. Port 2 and Port 1 IRIG-B circuits are in parallel; therefore,
connect only one IRIG-B source at a time.
Condition of Acceptability for North American Product Safety Compliance
To meet product safety compliance for end-use applications in North America, use an external
fuse rated 3 A or less in-line with the +5 Vdc source on Pin 1. SEL fiber-optic transceivers
include a fuse that meets this requirement.
Other Jumpers
Additional main board jumpers JMP5A through JMP5D, located near JMP6, are not functional
in the SEL-352 Relay. Originally they were installed for developmental testing purposes but are
not used in the production version of the relay. Jumpers must not be installed in any JMP5
position.
Low-Level Analog Interface
SEL designed the SEL-352 Relay main board to accept low-level analog signals as an optional
testing method.
Section 11: Testing and Troubleshooting contains a more detailed discussion of
the patented Low-Level Test Interface; Figure 11.1 shows the pin configuration. The SEL-RTS
(Relay Test System) interfaces with the relay through a ribbon cable connection on the main
board. With the front panel removed, the low-level interface connector is on the front edge at the
far right of the top board. Refer to Figure 2.16. Remove the ribbon cable from the main board
(top board), and connect the SEL-RTS ribbon cable to the main board. This removes the
connection from the transformers in the bottom of the relay chassis and connects the SEL-RTS
system for low-level testing. Refer to the SEL-RTS Instruction Manual for system operation.
For normal operation, be sure to properly reinstall the ribbon cable that connects the
transformers in the bottom of the chassis to the main board.
Clock Battery
Refer to Figure 2.16 for clock battery B1 location. This lithium battery powers the relay clock
(date and time) if the external power source is lost or removed. The battery is a 3 V lithium coin
cell. At room temperature (25
•
C) the battery will operate nominally for 10 years at rated load.