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CHAPTER  20   STANDBY  FUNCTION 

User’s Manual  U19780EJ2V0UD 

543

(2)  HALT mode release 

The HALT mode can be released by the following two sources. 

 

(a)  Release by unmasked interrupt request 

When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment 

is enabled, vectored interrupt servicing is carried out.  If interrupt acknowledgment is disabled, the next 

address instruction is executed. 

 

Figure 20-3.  HALT Mode Release by Interrupt Request Generation 

 

HALT

instruction

Wait

Note 1

Normal operation

HALT mode

Normal operation

Oscillation

High-speed system clock,

internal high-speed oscillation clock,

or subsystem clock

Note 2

Status of CPU

Standby

release signal

Interrupt

request

 

 

Notes 1.

  The wait time is as follows: 

 

 

  •  When vectored interrupt servicing is carried out: 

11 or 12 clocks 

 

 

  •  When vectored interrupt servicing is not carried out:  4 or 5 clocks 

 2.

  The 78K0/KB2-A is not provided with a subsystem clock. 

 

Remark

  The broken lines indicate the case when the interrupt request which has released the standby 

mode is acknowledged. 

 

Summary of Contents for 78K0 Series

Page 1: ...ook over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1st 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry ...

Page 2: ...ct for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communications equipment test and meas...

Page 3: ...Document No U19780EJ2V0UD00 2nd edition Date Published February 2010 NS Printed in Japan 2010 μPD78F0590 μPD78F0591 μPD78F0592 μPD78F0593 78K0 Kx2 A 8 Bit Single Chip Microcontrollers User s Manual ...

Page 4: ...User s Manual U19780EJ2V0UD 2 MEMO ...

Page 5: ...and measurement tools including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with mounted semiconductor devices 4 STATUS BEFORE INITIALIZATION Power on does not necessarily define the initial status of a MOS device Immediately after the powe...

Page 6: ...enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire contain...

Page 7: ...e CONTENTS How to interpret the register format For a bit number enclosed in angle brackets the bit name is defined as a reserved word in the RA78K0 and is defined as an sfr variable using the pragma sfr directive in the CC78K0 To know details of the 78K0 microcontroller instructions Refer to the separate document 78K 0 Series Instructions User s Manual U12326E Conventions Data significance Higher...

Page 8: ...2 94 Integrated Debugger User s Manual Operation U18330E ID78K0 QB Ver 3 00 Integrated Debugger User s Manual Operation U18492E PM plus Ver 5 20 Note 3 User s Manual U16934E PM Ver 6 30 Note 4 User s Manual U18416E Notes 1 This document is installed into the PC together with the tool when installing RA78K0 Ver 4 01 For descriptions not included in 78K0 Assembler Package RA78K0 Ver 4 01 Operating P...

Page 9: ...ocument Name Document No SEMICONDUCTOR SELECTION GUIDE Products and Packages X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD C11892E Note See the Semiconductor Device Mount Manual website http www nec...

Page 10: ...36 2 2 4 P31 to P35 port 3 37 2 2 5 P40 to P42 port 4 38 2 2 6 P60 P61 Port 6 39 2 2 7 P70 to P75 port 7 40 2 2 8 P80 to P83 port 8 40 2 2 9 P120 to P124 port 12 41 2 2 10 AVREF AVREFM AVREFP AVDD AVSS VDD VSS 42 2 2 11 RESET 43 2 2 12 REGC 43 2 2 13 FLMD0 43 2 3 Pin I O Circuits and Recommended Connection of Unused Pins 44 CHAPTER 3 CPU ARCHITECTURE 49 3 1 Memory Space 49 3 1 1 Internal program m...

Page 11: ... 2 6 Port 6 102 4 2 7 Port 7 104 4 2 8 Port 8 105 4 2 9 Port 12 109 4 3 Registers Controlling Port Function 113 4 4 Port Function Operations 119 4 4 1 Writing to I O port 119 4 4 2 Reading from I O port 120 4 4 3 Operations on I O port 120 4 5 Settings of Port Mode Register and Output Latch When Using Alternate Function 120 4 6 Cautions on 1 Bit Manipulation Instruction for Port Register n Pn 126 ...

Page 12: ...91 6 4 4 Operation in clear start mode entered by TI000 pin valid edge input 195 6 4 5 Free running timer operation 209 6 4 6 PPG output operation 218 6 4 7 One shot pulse output operation 221 6 4 8 Pulse width measurement operation 226 6 5 Special Use of TM00 234 6 5 1 Rewriting CR010 during TM00 operation 234 6 5 2 Setting LVS00 and LVR00 234 6 6 Cautions for 16 Bit Timer Event Counter 00 236 CH...

Page 13: ...imer 314 10 4 1 Controlling operation of watchdog timer 314 10 4 2 Setting overflow time of watchdog timer 315 10 4 3 Setting window open period of watchdog timer 316 CHAPTER 11 CLOCK OUTPUT CONTROLLER 318 11 1 Functions of Clock Output Controller 318 11 2 Configuration of Clock Output Controller 319 11 3 Registers Controlling Clock Output Controller 319 11 4 Operations of Clock Output Controller ...

Page 14: ...11 CHAPTER 16 SERIAL INTERFACE IICA 423 16 1 Functions of Serial Interface IICA 423 16 2 Configuration of Serial Interface IICA 426 16 3 Registers Controlling Serial Interface IICA 429 16 4 I2 C Bus Mode Functions 442 16 4 1 Pin configuration 442 16 4 2 Setting transfer clock by using IICWL and IICWH registers 443 16 5 I2 C Bus Definitions and Control Methods 445 16 5 1 Start conditions 445 16 5 2...

Page 15: ...KEY INTERRUPT FUNCTION 534 19 1 Functions of Key Interrupt 534 19 2 Configuration of Key Interrupt 535 19 3 Register Controlling Key Interrupt 536 CHAPTER 20 STANDBY FUNCTION 537 20 1 Standby Function and Configuration 537 20 1 1 Standby function 537 20 1 2 Registers controlling standby function 538 20 2 Standby Function Operation 540 20 2 1 HALT mode 540 20 2 2 STOP mode 545 CHAPTER 21 RESET FUNC...

Page 16: ...597 25 6 Programming Method 598 25 6 1 Controlling flash memory 598 25 6 2 Flash memory programming mode 598 25 6 3 Selecting communication mode 599 25 6 4 Communication commands 600 25 7 Security Settings 601 25 8 Flash Memory Programming by Self Programming 603 25 8 1 Boot swap function 610 CHAPTER 26 ON CHIP DEBUG FUNCTION 612 26 1 Connecting QB MINI2 to 78K0 Kx2 A microcontrollers 612 26 2 Res...

Page 17: ...User s Manual U19780EJ2V0UD 15 29 2 78K0 KC2 A 655 CHAPTER 30 CAUTIONS FOR WAIT 656 30 1 Cautions for Wait 656 30 2 Peripheral Hardware That Generates Wait 656 ...

Page 18: ...C circuit and low voltage detector LVI On chip watchdog timer operable with the on chip internal low speed oscillation clock On chip multiplier divider 16 bits 16 bits 32 bits 16 bits On chip key interrupt function 6 channels 78K0 KC2 A only On chip clock output controller 78K0 KC2 A only I O ports 78K0 KB2 A 22 N ch open drain 2 78K0 KC2 A 40 N ch open drain 2 On chip 12 bit resolution A D conver...

Page 19: ...on lead free product 78K0 Kx2 A microcontrollers Package Part Number 78K0 KB2 A 30 pin plastic SSOP 7 62 mm 300 μPD78F0590MC CAB AX 78F0591MC CAB AX 78K0 KC2 A 48 pin plastic LQFP fine pitch 7x7 μPD78F0592GA GAM AX 78F0593GA GAM AX Caution 78K0 Kx2 A microcontrollers have an on chip debug function which is provided for development and evaluation Do not use the on chip debug function in products de...

Page 20: ...VREF AVSS AVDD P80 ANI8 AMP2 P81 ANI9 AMP2OUT P82 ANI10 AMP2 P83 ANI11 P11 RxD6 TI50 TO50 P10 TxD6 TI51 TO51 P12 TOH0 INTP7 TI000 P13 TOH1 INTP6 TI010 TO00 P31 INTP5 OCD1A SCK10 P32 INTP4 OCD1B SI10 1 2 3 4 5 6 7 8 9 10 11 12 13 17 14 15 Cautions 1 Make AVSS the same potential as VSS 2 Connect the REGC pin to VSS via a capacitor 0 47 to 1 μF recommended Remark The functions of pins whose names are...

Page 21: ... Flash Programming Mode INTP0 INTP1 INTP4 to INTP7 External Interrupt Input OCD0A OCD0B OCD1A OCD1B On Chip Debug Input Output P10 to P13 Port 1 P20 to P25 Port 2 P31 P32 P35 Port 3 P60 P61 Port 6 P80 to P83 Port 8 P120 to P122 Port 12 REGC Regulator Capacitance RESET Reset RxD6 Receive Data SCK10 Serial Clock Input Output SCLA0 Serial Clock Input Output SDAA0 Serial Data Input Output SI10 Serial ...

Page 22: ...0 P23 ANI3 AMP1 P24 ANI4 AMP1OUT P25 ANI5 AMP1 P26 ANI6 P27 ANI15 AVREFM P31 INTP5 OCD1A SCK10 P13 TOH1 INTP6 P12 TOH0 INTP7 P11 RxD6 P10 TxD6 P83 ANI11 P82 ANI10 AMP2 P81 ANI9 AMP2OUT P80 ANI8 AMP2 AV DD AV SS AV REFP V DD V SS REGC P121 X1 OCD0A P122 X2 EXCLK OCD0B FLMD0 P123 XT1 P124 XT2 RESET P40 RTCCL RTCDIV P41 RTC1HZ P120 INTP0 EXLVI Cautions 1 Make AVSS the same potential as VSS 2 Connect ...

Page 23: ...P10 to P13 Port 1 P20 to P27 Port 2 P31 to P35 Port 3 P40 to P42 Port 4 P60 P61 Port 6 P70 to P75 Port 7 P80 to P83 Port 8 P120 to P124 Port 12 PCL Programmable Clock Output REGC Regulator Capacitance RESET Reset RTC1HZ Real time Counter Correction Clock 1 Hz Output RTCCL Real time Counter Clock 32 kHz Original Oscillation Output RTCDIV Real time Counter Clock 32 kHz Divided Frequency Output RxD6 ...

Page 24: ...121 X2 EXCLK P122 ON CHIP DEBUG OCD0A X1 OCD1A P31 OCD0B X2 OCD1B P32 VOLTAGE REGULATOR REGC INTERNAL HIGH SPEED OSCILLATOR INTERNAL LOW SPEED OSCILLATOR PORT 8 P80 to P83 4 A D CONVERTER ANI0 P20 to ANI5 P25 ANI8 P80 to ANI11 P83 AVDD AVSS OP AMP 0 AMP0 P20 AMP0OUT P21 AMP0 P22 OP AMP 1 AMP1 P23 AMP1OUT P24 AMP1 P25 AVREF 10 OP AMP 2 AMP2 P80 AMP2OUT P81 AMP2 P82 MULTIPLIER DIVIDER SERIAL INTERFA...

Page 25: ...NAL LOW SPEED OSCILLATOR PORT 8 P80 to P83 4 A D CONVERTER ANI0 P20 to ANI6 P26 ANI8 P80 to ANI11 P83 ANI15 P27 AVDD AVSS OP AMP 0 AMP0 P20 AMP0OUT P21 AMP0 P22 OP AMP 1 AMP1 P23 AMP1OUT P24 AMP1 P25 AVREFP 12 OP AMP 2 AMP2 P80 AMP2OUT P81 AMP2 P82 MULTIPLIER DIVIDER PORT 0 P00 to P02 3 PORT 4 P40 to P42 3 PORT 7 P70 to P75 6 AVREFM P27 XT1 P123 XT2 P124 REALTIME COUNTER RTC1HZ P41 RTCDIV RTCCL P4...

Page 26: ...ks Total 22 40 CMOS I O 20 38 Port N ch I O 2 2 16 bits TM0 1 ch PPG output 1 Capture trigger input 2 8 bits TM5 2 ch PWM output 2 8 bits TMH 2 ch PWM output 2 Watchdog timer WDT 1 ch Timer Real time counter 1 ch RTC output 2 Clock output 1 3 wire CSI 1 ch Note 1 1 ch Notes 1 2 UART supporting LIN bus 1 ch Serial interface I2 C 1 ch 12 bit A D converter 10 ch 12 ch Operational amplifier 3 ch Exter...

Page 27: ...pplies AVDD and VDD The relationship between these power supplies and the pins is shown below Table 2 1 Pin I O Buffer Power Supplies Corresponding Pins Power Supply 78K0 KB2 A 78K0 KC2 A AVDD P20 to P25 P80 to P83 P20 to P27 P80 to P83 VDD Pins other than P20 to P25 and P80 to P83 Pins other than P20 to P27 and P80 to P83 ...

Page 28: ... Port 3 3 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input port SO10 INTP1 P60 SCLA0 SCK10 P61 I O Port 6 2 bit I O port Output is N ch open drain output 6 V tolerance Input output can be specified in 1 bit units Input port SDAA0 SI10 P80 ANI8 AMP2 P81 ANI9 AMP2OUT P82 ANI10 AMP2 P83 I O Port 8 4 bit I O port ...

Page 29: ...for external low voltage detection Input port P120 INTP0 FLMD0 Flash memory programming mode setting INTP0 P120 EXLVI INTP1 P35 SO10 INTP4 P32 OCD1B SI10 INTP5 P31 OCD1A SCK10 INTP6 P13 TOH1 TI010 TO00 INTP7 Input External interrupt request input for which the valid edge rising edge falling edge or both rising and falling edges can be specified Input port P12 TOH0 TI000 REGC Connecting regulator o...

Page 30: ...imer event counter 51 output Input port P10 TI51 TxD6 TOH0 8 bit timer H0 output P12 TI000 INTP7 TOH1 Output 8 bit timer H1 output Input port P13 TI010 TO00 INTP6 TxD6 Output Serial data output from UART6 Input port P10 TI51 TO51 X1 Input port P121 OCD0A X2 Connecting resonator for main system clock Input port P122 EXCLK OCD0B EXCLK Input External clock input for main system clock Input port P122 ...

Page 31: ...t ANI15 AVREFM P31 INTP5 OCD1A SCK10 P32 INTP4 OCD1B SI10 P33 TI51 TO51 INTP3 P34 TI50 TO50 INTP2 P35 I O Port 3 5 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input port SO10 INTP1 P40 RTCCL RTCDIV P41 RTC1HZ P42 I O Port 4 3 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up re...

Page 32: ...NI9 AMP2OUT P82 ANI10 AMP2 P83 I O Port 8 4 bit I O port Input output can be specified in 1 bit units Digital input port ANI11 P120 INTP0 EXLVI P121 X1 OCD0A P122 X2 EXCLK OCD0B P123 XT1 P124 I O Port 12 5 bit I O port Input output can be specified in 1 bit units Only for P120 use of an on chip pull up resistor can be specified by a software setting Input port XT2 ...

Page 33: ... analog reference voltage minus Digital input port ANI15 P27 AVREFP Input A D converter analog reference voltage plus Analog input EXLVI Input Potential input for external low voltage detection Input port P120 INTP0 FLMD0 Flash memory programming mode setting INTP0 P120 EXLVI INTP1 P35 SO10 INTP2 P34 TI50 TO50 INTP3 P33 TI51 TO51 INTP4 P32 OCD1B SI10 INTP5 P31 OCD1A SCK10 INTP6 P13 TOH1 INTP7 P12 ...

Page 34: ... PCL INTP9 TI000 Input External count clock input to 16 bit timer event counter 00 Capture trigger input to capture registers CR000 CR010 of 16 bit timer event counter 00 Input port P00 TI010 Input Capture trigger input to capture register CR000 of 16 bit timer event counter 00 Input port P01 TO00 TI50 External count clock input to 8 bit timer event counter 50 P34 TO50 INTP2 TI51 Input External co...

Page 35: ... operational amplifier VSS Ground potential for pins other than P20 to P27 P80 to P83 A D converter and operational amplifier AVSS Ground potential for pins P20 to P27 P80 to P83 A D converter and operational amplifier Make the same potential as VSS OCD0A P121 X1 OCD1A Input P31 INTP5 SCK10 OCD0B P122 X2 EXCLK OCD1B I O Connection for on chip debug mode setting pins Input port P32 INTP4 SI10 Remar...

Page 36: ...mode register 0 PM0 Use of an on chip pull up resistor can be specified by pull up resistor option register 0 PU0 2 Control mode P00 to P02 function as external interrupt request input and timer I O a INTP8 There is external interrupt request input pin for which the valid edge rising edge falling edge or both rising and falling edges can be specified b TI000 There is the pin for inputting an exter...

Page 37: ...ontrol mode P10 to P13 function as external interrupt request input serial interface data I O and timer I O a INTP6 INTP7 These are external interrupt request input pins for which the valid edge rising edge falling edge or both rising and falling edges can be specified b RxD6 This is a serial data input pin of serial interface UART6 c TxD6 This is a serial data output pin of serial interface UART6...

Page 38: ...egister 2 PM2 2 Control mode P20 to P27 function as pins for A D converter analog input anarog reference voltage input and operational amplifier output a ANI0 to ANI6 ANI15 P20 to P27 function as A D converter analog input pins When using these pins as analog input pins see 5 ANI0 to ANI6 ANI8 to ANI11 and ANI15 in 12 6 Cautions for A D Converter b AVREFM This is an analog reference voltage input ...

Page 39: ...t or output port in 1 bit units using port mode register 3 PM3 Use of an on chip pull up resistor can be specified by pull up resistor option register 3 PU3 2 Control mode P31 to P35 function as external interrupt request input serial interface data I O clock I O and timer I O a INTP1 to INTP5 These are the external interrupt request input pins for which the valid edge rising edge falling edge or ...

Page 40: ...rnal interrupt request input clock output real time counter clock output and chip select input for serial interface 78K0 KB2 A 78K0 KC2 A P40 RTCCL RTCDIV P41 RTC1HZ P42 PCL SSI10 INTP9 The following operation modes can be specified in 1 bit units 1 Port mode P40 to P42 function as an I O port P40 to P42 can be set to input or output port in 1 bit units using port mode register 4 PM4 Use of an on ...

Page 41: ...ng operation modes can be specified in 1 bit units 1 Port mode P60 and P61 function as an I O port P60 and P61 can be set to input or output port in 1 bit units using port mode register 6 PM6 Output of P60 and P61 is N ch open drain output 6 V tolerance 2 Control mode P60 and P61 function as serial interface data I O and clock I O a SI10 This is a serial data input pin to serial interface CSI10 b ...

Page 42: ... pull up resistor option register 7 PU7 2 Control mode P70 to P75 function as key interrupt input pins a KR0 to KR5 These are the key interrupt input pins 2 2 8 P80 to P83 port 8 P80 to P83 function as an I O port These pins also function as A D converter reference analog input and operational amplifier I O 78K0 KB2 A 78K0 KC2 A P80 ANI8 AMP2 P81 ANI9 AMP2OUT P82 ANI10 AMP2 P83 ANI11 The following...

Page 43: ...xternal clock input for main system clock 78K0 KB2 A 78K0 KC2 A P120 INTP0 EXLVI P121 X1 OCD0A P122 X2 OCD0B P123 XT1 P124 XT2 The following operation modes can be specified in 1 bit units 1 Port mode P120 to P124 function as an I O port P120 to P124 can be set to input or output port using port mode register 12 PM12 Only for P120 use of an on chip pull up resistor can be specified by pull up resi...

Page 44: ...lator connection when it is not used as an on chip debug mode setting pin During reset released Input Connect to VDD or VSS via a resistor Output Leave open Remark X1 and X2 can be used as on chip debug mode setting pins OCD0A and OCD0B when the on chip debug function is used For how to connect an on chip debug emulator QB MINI2 see CHAPTER 26 ON CHIP DEBUG FUNCTION 2 2 10 AVREF AVREFM AVREFP AVDD...

Page 45: ... f VDD VDD is the positive power supply pin for other than P20 to P27 P80 to P83 A D converter and operational amplifier g VSS VSS is the ground potential pin for other than P20 to P27 P80 to P83 A D converter and operational amplifier 2 2 11 RESET This is the active low system reset input pin 2 2 12 REGC This is the pin for connecting regulator output 2 5 V stabilization capacitance for internal ...

Page 46: ...ended Connection of Unused Pins P00 TI000 P01 TI010 TO00 P02 INTP8 P10 TxD6Note P11 RxD6Note P12 TOH0 INTP7Note P13 TOH1 INTP6Note 5 AQ Input Independently connect to VDD or VSS via a resistor Output Leave open P20 ANI0 AMP0 11 P P21 ANI1 AMP0OUT 11 S P22 ANI2 AMP0 11 N P23 ANI3 AMP1 11 P P24 ANI4 AMP1OUT 11 S P25 ANI5 AMP1 11 N P26 ANI6 11 G P27 ANI15 AVREFM 11 T I O Digital input setting and ana...

Page 47: ...s 1 2 P122 X2 EXCLK OCD0BNote 2 P123 XT1Note 2 P124 XT2Note 2 37 I O Input Independently connect to VDD or VSS via a resistor Output Leave open AVREFP Make the same potential as the AVDD or VDD Note 3 Notes 1 Process the P31 INTP5 OCD1A SCK10 and P121 X1 OCD0A pins as follows when it is not used when it is connected to a flash memory programmer or an on chip debug emulator P31 INTP5 OCD1A SCK10 P1...

Page 48: ...P80 to P83 are specified as analog ports Specify a potential that satisfies the condition AVREFP VDD AVSS Make the same potential as the VSS FLMD0 38 A Connect to VSS Note RESET 2 Input Connect directly to VDD or via a resistor Note FLMD0 is a pin that is used to write data to the flash memory To rewrite the data of the flash memory on board connect this pin to VSS via a resistor 10 kΩ recommended...

Page 49: ...5 AQ pullup enable data output disable input enable VDD P ch VDD P ch IN OUT N ch VSS data output disable AVDD P ch IN OUT N ch P ch N ch input enable _ AVSS AVSS Comparator Series resistor string voltage Type 11 N Type 11 P data output disable AVDD P ch IN OUT N ch P ch N ch input enable _ AVSS AVSS _ OP AMP VREF threshold voltage Comparator data output disable AVDD P ch IN OUT N ch P ch N ch inp...

Page 50: ...MP VREF threshold voltage Comparator data output disable AVDD P ch IN OUT N ch P ch N ch input enable _ AVSS AVSS VREF threshold voltage P ch N ch AVREFM Comparator Type 13 AI Type 37 data output disable input enable IN OUT N ch VSS Type 38 A input enable IN reset reset data output disable input enable VDD P ch X1 XT1 N ch VSS data output disable input enable VDD P ch N ch VSS P ch N ch X2 XT2 ...

Page 51: ...apacity the initial values of the internal memory size switching register IMS of 78K0 Kx2 A microcontrollers are fixed IMS CFH Therefore set the value corresponding to each product as indicated below Table 3 1 Set Values of Internal Memory Size Switching Register IMS Part Number 78K0 KB2 A 78K0 KC2 A IMS ROM Capacity Internal High Speed RAM Capacity μPD78F0590 μPD78F0592 C4H 16 KB μPD78F0591 μPD78...

Page 52: ...lock Numbers in Flash Memory Block 00H Block 01H Block 0FH 1 KB 3 F F F H 0 7 F F H 0 0 0 0 H 0 4 0 0 H 0 3 F F H 3 C 0 0 H 3 B F F H Data memory space Program memory space 0000H 4000H 3FFFH FB00H FAFFH FFFFH FF00H FEFFH FEE0H FEDFH Flash memory 16384 8 bits Reserved Internal high speed RAM 1024 8 bits General purpose registers 32 8 bits Special function registers SFR 256 8 bits 3FFFH 0800H 07FFH ...

Page 53: ... Option byte areaNote 1 5 8 bits CALLF entry area 2048 8 bits On chip debug security ID setting areaNote 1 10 8 bits 1FFFH Boot cluster 1 Boot cluster 0Note 2 Program area Notes 1 When boot swap is not used Set the option bytes to 0080H to 0084H and the on chip debug security IDs to 0085H to 008EH When boot swap is used Set the option bytes to 0080H to 0084H and 1080H to 1084H and the on chip debu...

Page 54: ...H 09H 6400H to 67FFH 19H 2800H to 2BFFH 0AH 6800H to 6BFFH 1AH 2C00H to 2FFFH 0BH 6C00H to 6FFFH 1BH 3000H to 33FFH 0CH 7000H to 73FFH 1CH 3400H to 37FFH 0DH 7400H to 77FFH 1DH 3800H to 3BFFH 0EH 7800H to 7BFFH 1EH 3C00H to 3FFFH 0FH 7C00H to 7FFFH 1FH Remark μPD78F0590 78F0592 Block numbers 00H to 0FH μPD78F0591 78F0593 Block numbers 00H to 1FH 3 1 1 Internal program memory space The internal pro...

Page 55: ... Interrupt Source 78K0 KB2 A μPD78F0590 78F0591 78K0 KC2 A μPD78F0592 78F0593 0000H RESET input POC LVI WDT 0004H INTLVI 0006H INTP0 0008H INTP1 000AH INTP2 000CH INTP3 000EH INTP4 0010H INTP5 0012H INTSRE6 0014H INTSR6 0016H INTST6 0018H INTCSI10 001AH INTTMH1 001CH INTTMH0 001EH INTTM50 0020H INTTM000 0022H INTTM010 0024H INTAD 0026H INTIICA0 0028H INTRTCI 002AH INTTM51 002CH INTKR 002EH INTRTC ...

Page 56: ...gram area in which instructions are written and executed The internal high speed RAM can also be used as a stack memory Table 3 5 Internal High Speed RAM Capacity Part Number 78K0 KB2 A 78K0 KC2 A Internal High Speed RAM μPD78F0590 μPD78F0592 μPD78F0591 μPD78F0593 1024 8 bits FB00H to FEFFH 3 1 3 Special function register SFR area On chip peripheral hardware special function registers SFRs are all...

Page 57: ... addressing Based addressing Based indexed addressing Special function registers SFR 256 x 8 bits Internal high speed RAM 1024 x 8 bits General purpose registers 32 x 8 bits Reserved Flash memory 16384 x 8 bits F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F B 0 0 H F A F F H 4 0 0 0 H 3 F F F H 0 0 0 0 H F F 2 0 H F F 1 F H F E 2 0 H F E 1 F H Register addressing Short direct addressing ...

Page 58: ... addressing Based addressing Based indexed addressing Special function registers SFR 256 x 8 bits Internal high speed RAM 1024 x 8 bits General purpose registers 32 x 8 bits Reserved Flash memory 32768 x 8 bits F F F F H F F 0 0 H F E F F H F E E 0 H F E D F H F B 0 0 H F A F F H 8 0 0 0 H 7 F F F H 0 0 0 0 H F F 2 0 H F F 1 F H F E 2 0 H F E 1 F H Register addressing Short direct addressing ...

Page 59: ...am status word PSW The program status word is an 8 bit register consisting of various flags set reset by instruction execution Program status word contents are stored in the stack area upon vectored interrupt request acknowledgement or PUSH PSW instruction execution and are restored upon execution of the RETB RETI and POP PSW instructions Reset signal generation sets PSW to 02H Figure 3 6 Format o...

Page 60: ... PR1H can not be acknowledged Actual request acknowledgment is controlled by the interrupt enable flag IE f Carry flag CY This flag stores overflow and underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution 3 Stack pointer SP This is a 16 bit register to hold the...

Page 61: ...truction when SP FEE0H Register pair lower FEE0H SP SP FEE0H FEDFH FEDEH Register pair higher FEDEH b CALL CALLF CALLT instructions when SP FEE0H PC15 to PC8 FEE0H SP SP FEE0H FEDFH FEDEH PC7 to PC0 FEDEH c Interrupt BRK instructions when SP FEE0H PC15 to PC8 PSW FEDFH FEE0H SP SP FEE0H FEDEH FEDDH PC7 to PC0 FEDDH ...

Page 62: ...dresses FEE0H to FEFFH of the data memory The general purpose registers consists of 4 banks each bank consisting of eight 8 bit registers X A C B E D L and H Each register can be used as an 8 bit register and two 8 bit registers can also be used in a pair as a 16 bit register AX BC DE and HL These registers can be described in terms of function names X A C B E D L H AX BC DE and HL and absolute na...

Page 63: ...0 Register bank 1 Register bank 2 Register bank 3 FEFFH FEF8H FEE0H HL DE BC AX H 15 0 7 0 L D E B C A X 16 bit processing 8 bit processing FEF0H FEE8H b Absolute name Register bank 0 Register bank 1 Register bank 2 Register bank 3 FEFFH FEF8H FEE0H RP3 RP2 RP1 RP0 R7 15 0 7 0 R6 R5 R4 R3 R2 R1 R0 16 bit processing 8 bit processing FEF0H FEE8H ...

Page 64: ...on operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved by the assembler for the 16 bit manipulation instruction operand sfrp When specifying an address describe an even address Table 3 6 gives a list of the special function registers The meanings of items in the table are as follows Symbol Symbol indicating the address of a special f...

Page 65: ...11H 16 bit timer counter 00 TM00 R 0000H FF12H FF13H 16 bit timer capture compare register 000 CR000 R W 0000H FF14H FF15H 16 bit timer capture compare register 010 CR010 R W 0000H FF16H 8 bit timer counter 50 TM50 R 00H FF17H 8 bit timer compare register 50 CR50 R W 00H FF18H 12 bit A D conversion result register ADCR R 0000H FF19H 8 bit A D conversion result register ADCRH R 00H FF1AH 8 bit time...

Page 66: ... 00H FF43H 8 bit timer mode control register 51 TMC51 R W 00H FF48H External interrupt rising edge enable register 0 EGP0 R W 00H FF49H External interrupt falling edge enable register 0 EGN0 R W 00H FF4AH External interrupt rising edge enable register 1 EGP1 R W 00H FF4BH External interrupt falling edge enable register 1 EGN1 R W 00H FF4FH Input switch control register ISC R W 00H FF50H Asynchrono...

Page 67: ...H FF7BH Alarm hour register ALARMWH R W 12H FF7CH Alarm week register ALARMWW R W 00H FF7DH Real time counter control register 0 RTCC0 R W 00H FF7EH Real time counter control register 1 RTCC1 R W 00H FF7FH Real time counter control register 2 RTCC2 R W 00H FF80H Serial operation mode register 10 CSIM10 R W 00H FF81H Serial clock selection register 10 CSIC10 R W 00H FF84H Transmit buffer register 1...

Page 68: ...ter LVIS R W 00HNote 2 FFE0H Interrupt request flag register 0L IF0L R W 00H FFE1H Interrupt request flag register 0H IF0 IF0H R W 00H FFE2H Interrupt request flag register 1L IF1L R W 00H FFE3H Interrupt request flag register 1H IF1 IF1H R W 00H FFE4H Interrupt mask flag register 0L MK0L R W FFH FFE5H Interrupt mask flag register 0H MK0 MK0H R W FFH FFE6H Interrupt mask flag register 1L MK1L R W ...

Page 69: ...e addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transferred to the program counter PC and branched The displacement value is treated as signed two s complement data 128 to 127 and bit 7 becomes a sign bit In other words relative addressing consists of relative branching fro...

Page 70: ... CALL addr16 or BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can be branched to the entire memory space The CALLF addr11 instruction is branched to the 0800H to 0FFFH area Illustration In the case of CALL addr16 and BR addr16 instructions 15 0 PC 8 7 7 0 CALL or BR Low Addr High Addr In the case of CALLF addr11 instruction 15 0 PC 8 7 7 0 fa10 8 11 10 0 ...

Page 71: ... is carried out when the CALLT addr5 instruction is executed This instruction references the address that is indicated by addr5 and is stored in the memory table from 0040H to 007FH and allows branching to the entire memory space Illustration 15 1 15 0 PC 7 0 Low Addr High Addr Memory Table Effective address 1 Effective address 0 1 0 0 0 0 0 0 0 0 8 7 8 7 6 5 0 0 1 1 1 7 6 5 1 0 ta4 0 Operation co...

Page 72: ... implicitly addressed Of the 78K0 Kx2 A microcontrollers instruction words the following instructions employ implied addressing Instruction Register to Be Specified by Implied Addressing MULU A register for multiplicand and AX register for product storage DIVUW AX register for dividend and quotient storage ADJBA ADJBS A register for storage of numeric values that become decimal correction targets ...

Page 73: ...erand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E D L H rp AX BC DE HL r and rp can be described by absolute names R0 to R7 and RP0 to RP3 as well as function names X A C B E D L H AX BC DE and HL Description example MOV A C when selecting C register as r Operation...

Page 74: ...tion word becoming an operand address This addressing can be carried out for all of the memory spaces Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Operation code 1 0 0 0 1 1 1 0 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH Illustration Memory 0 7 addr16 lower addr16 upper OP code ...

Page 75: ...wing SFRs to be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to 0 When it is at 00H to 1FH bit 8 is set to 1 See the Illustration shown below Operand format Identifier Description saddr Immediate data that indicate label or FE20H to FF1FH saddrp Immediate data that indicate label or FE20H to FF1FH even address o...

Page 76: ... to FFCFH and FFE0H to FFFFH However the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit manipulatable special function register name even address only Description example MOV PM0 A when selecting PM0 FF20H as sfr Operation code 1 1 1 1 0 1 1 0 OP code 0 0 1 0 0 0 0 0 20H sfr offset Illu...

Page 77: ... RBS0 and RBS1 serve as an operand address for addressing the memory This addressing can be carried out for all of the memory spaces Operand format Identifier Description DE HL Description example MOV A DE when selecting DE as register pair Operation code 1 0 0 0 0 1 0 1 Illustration 16 0 8 D 7 E 0 7 7 0 A DE The contents of the memory addressed are transferred Memory The memory address specified ...

Page 78: ... and the sum is used to address the memory Addition is performed by expanding the offset data as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all of the memory spaces Operand format Identifier Description HL byte Description example MOV A HL 10H when setting byte to 10H Operation code 1 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 Illustration 16 0 8 H ...

Page 79: ...lag RBS0 and RBS1 and the sum is used to address the memory Addition is performed by expanding the B or C register contents as a positive number to 16 bits A carry from the 16th bit is ignored This addressing can be carried out for all of the memory spaces Operand format Identifier Description HL B HL C Description example MOV A HL B when selecting B register Operation code 1 0 1 0 1 0 1 1 Illustr...

Page 80: ...s automatically employed when the PUSH POP subroutine call and return instructions are executed or the register is saved reset upon generation of an interrupt request With stack addressing only the internal high speed RAM area can be accessed Description example PUSH DE when saving DE register Operation code 1 0 1 1 0 1 0 1 Illustration E FEE0H SP SP FEE0H FEDFH FEDEH D Memory 0 7 FEDEH ...

Page 81: ...Supply 78K0 KB2 A 78K0 KC2 A AVDD P20 to P25 P80 to P83 P20 to P27 P80 to 83 VDD Pins other than P20 to P25 P80 to P83 Pins other than P20 to P27 P80 to 83 78K0 Kx2 A microcontrollers are provided with digital I O ports which enable variety of control operations The functions of each port are shown in Tables 4 2 and 4 3 In addition to the function as digital I O ports these ports have several alte...

Page 82: ...t 3 3 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input port SO10 INTP1 P60 SCLA0 SCK10 P61 I O Port 6 2 bit I O port Output is N ch open drain output 6 V tolerance Input output can be specified in 1 bit units Input port SDAA0 SI10 P80 ANI8 AMP2 P81 ANI9 AMP2OUT P82 ANI10 AMP2 P83 I O Port 8 4 bit I O port Inpu...

Page 83: ...resistor can be specified by a software setting Input port SO10 INTP1 P40 RTCCL RTCDIV P41 RTC1HZ P42 I O Port 4 3 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting Input port PCL SSI10 INTP9 P60 SCLA0 SCK10 P61 I O Port 6 2 bit I O port Output is N ch open drain output 6 V tolerance Input output can be specified in ...

Page 84: ... P6 P8 P12 Pull up resistor option register PUxx PU1 PU3 PU12 A D port configuration register ADPC 78K0 KC2 A Port mode register PMxx PM0 to PM4 PM6 to PM8 PM12 Port register Pxx P0 to P4 P6 to P8 P12 Pull up resistor option register PUxx PU0 PU1 PU3 PU4 PU7 PU12 A D port configuration register ADPC Port 78K0 KB2 A Total 22 CMOS I O 20 N ch open drain I O 2 78K0 KC2 A Total 40 CMOS I O 38 N ch ope...

Page 85: ...tor can be specified in 1 bit units by pull up resistor option register 0 PU0 This port can also be used for external interrupt request input t and timer I O Reset signal generation sets port 0 to input mode Figures 4 1 and 4 2 show block diagrams of port 0 Figure 4 1 Block Diagram of P00 P02 P00 TI000 P02 INTP8 WRPU RD PU0 PM0 WRPORT WRPM PU00 PU02 Output latch P00 P02 PM00 PM02 VDD P ch P0 Alter...

Page 86: ...k Diagram of P01 P01 TI010 TO00 WRPU RD WRPORT WRPM PU01 Alternate function Output latch P01 PM01 Alternate function VDD P ch Selector Internal bus PU0 PM0 P0 P0 Port register 0 PU0 Pull up resistor option register 0 PM0 Port mode register 0 RD Read signal WR Write signal ...

Page 87: ...port mode register 1 PM1 When the P10 to P13 pins are used as an input port use of an on chip pull up resistor can be specified in 1 bit units by pull up resistor option register 1 PU1 This port can also be used for external interrupt request input serial interface data I O and timer I O Reset signal generation sets port 1 to input mode Figures 4 3 to 4 5 show block diagrams of port 1 Cautions To ...

Page 88: ... A WRPU RD WRPORT WRPM PU10 Output latch P10 PM10 P10 TxD6 TI51 TO51 VDD P ch PU1 PM1 P1 Alternate function Timer Alternate function Serial interface Alternate function Internal bus Selector P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 89: ...gram of P10 2 2 2 78K0 KC2 A P10 TxD6 WRPU RD WRPORT WRPM PU10 PM10 VDD P ch PU1 PM1 P1 Internal bus Output latch P10 Selector Alternate function Alternate function P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 90: ...of P11 1 2 1 78K0 KB2 A WRPU RD WRPORT WRPM PU11 PM11 VDD P ch PM1 PU1 P1 P11 RxD6 TI50 TO50 Internal bus Output latch P11 Alternate function Alternate function Selector P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 91: ...Block Diagram of P11 2 2 2 78K0 KC2 A P11 RxD6 WRPU RD WRPORT WRPM PU11 PM11 VDD P ch PU1 PM1 P1 Internal bus Selector Alternate function Output latch P11 P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 92: ...1 P12 TOH0 INTP7 TI000Note P13 TOH1 INTP6 TI010 TO00Note Internal bus Output latch P12 P13 Alternate function Alternate function Selector P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal Note 78K0 KB2 A P12 TOH0 INTP7 TI000 P13 TOH1 INTP6 TI010 TO00 78K0 KC2 A P12 TOH0 INTP7 P13 TOH1 INTP6 ...

Page 93: ...t analog reference voltage input and operational amplifier I O When using P20 ANI0 AMP0 to P27 ANI15 AVREFM set the registers according to the pin function to be used refer to Tables 4 5 to 4 8 To use P20 ANI0 AMP0 to P27 ANI15 AVREFM and P80 ANI8 AMP2 to P83 ANI11 as a digital input or a digital output it is recommended to select a pin to use starting with the furthest P20 ANI0 AMP0 pin from AVDD...

Page 94: ...0OUT P24 ANI4 AMP1OUT Pin 0 Digital input Input mode 1 Setting prohibited 0 Digital output Digital I O selection Output mode 1 Setting prohibited Selects ANI Analog input to be converted 0 Does not select ANI Analog input not to be converted Selects ANI Operational amplifier output to be converted Input mode 1 Does not select ANI Operational amplifier output not to be converted Analog input select...

Page 95: ...mode 1 Setting prohibited 0 Digital output Digital I O selection Output mode 1 Setting prohibited Selects ANI Analog input to be converted 0 Does not select ANI Analog input not to be converted Input mode 1 Reference voltage input on the negative side of A D converter Analog input selection Output mode Setting prohibited Figures 4 6 to 4 10 show block diagrams of port 2 ...

Page 96: ...2 P2 A D converter Operational amplifier input Internal bus Selector Output latch P20 P23 Figure 4 7 Block Diagram of P21 P24 P21 ANI1 AMP0OUT P24 ANI4 AMP1OUT RD WRPORT WRPM PM21 PM24 PM2 P2 A D converter Operational amplifier output Internal bus Selector Output latch P21 P24 P2 Port register 2 PM2 Port mode register 2 RD Read signal WR Write signal ...

Page 97: ...AMP1 RD WRPORT WRPM PM22 PM25 PM2 P2 Internal bus Selector Output latch P22 P25 A D converter Operational amplifier input Figure 4 9 Block Diagram of P26 P26 ANI6 RD WRPORT WRPM PM26 PM2 P2 Internal bus A D converter Selector Output latch P26 P2 Port register 2 PM2 Port mode register 2 RD Read signal WR Write signal ...

Page 98: ...EJ2V0UD 96 Figure 4 10 Block Diagram of P27 P27 ANI15 AVREFM RD WRPORT WRPM PM27 PM2 P2 Internal bus Selector Output latch P27 A D converter Analog reference voltage input P2 Port register 2 PM2 Port mode register 2 RD Read signal WR Write signal ...

Page 99: ...I O Reset signal generation sets port 3 to input mode Figures 4 11 and 4 13 show block diagrams of port 3 Cautions 1 Process the P31 INTP5 OCD1A SCK10 pin as follows when it is not used when it is connected to a flash memory programmer or an on chip debug emulator P31 INTP5 OCD1A SCK10 Flash memory programmer connection During reset Connect to VSS via a resistor On chip debug emulator connection w...

Page 100: ...te function Figure 4 12 Block Diagram of P32 P32 INTP4 OCD1B SI10 WRPU RD WRPORT WRPM PU32 PM32 VDD P ch PU3 PM3 P3 Internal bus Selector Alternate function Output latch P32 P3 Port register 3 PU3 Pull up resistor option register 3 PM3 Port mode register 3 RD Read signal WR Write signal Remark The functions of pins whose names are in parentheses can be used by setting bit 2 ISC2 of the input switc...

Page 101: ...TI51 TO51 P34 INTP2 TI50 TO50 P35 INTP1 SO10 WRPU RD WRPORT WRPM PU33 to PU35 PM33 to PM35 VDD P ch PU3 PM3 P3 Internal bus Selector Alternate function Alternate function Output latch P33 to P35 P3 Port register 3 PU3 Pull up resistor option register 3 PM3 Port mode register 3 RD Read signal WR Write signal ...

Page 102: ...by pull up resistor option register 4 PU4 This port can also be used for external interrupt request input clock output real time counter clock output and chip select input for serial interface Reset signal generation sets port 4 to input mode Figures 4 14 and 4 15 show block diagrams of port 4 Figure 4 14 Block Diagram of P40 and P41 P40 RTCCL RTCDIV P41 RTC1HZ WRPU RD WRPORT WRPM PU40 PU41 PM40 P...

Page 103: ... Diagram of P42 WRPU RD WRPORT WRPM PU42 PM42 VDD P ch PM4 PU4 P4 P42 PCL SSI10 INTP9 Internal bus Selector Alternate function Alternate function Output latch P42 P4 Port register 4 PU4 Pull up resistor option register 4 PM4 Port mode register 4 RD Read signal WR Write signal ...

Page 104: ...sing port mode register 6 PM6 The output of the P60 and P61 pins is N ch open drain output 6 V tolerance This port can also be used for serial interface data I O and clock I O Reset signal generation sets port 6 to input mode Figures 4 16 shows block diagram of port 6 Caution To use P60 SCK10 as general purpose ports set serial operation mode register 10 CSIM10 and serial clock selection register ...

Page 105: ...function Alternate function Output latch P60 P61 P6 Port register 6 PM6 Port mode register 6 RD Read signal WR Write signal Caution A through current flows through P60 and P61 if an intermediate potential is input to these pins because the input buffer is also turned on when P60 and P61 are in output mode Consequently do not input an intermediate potential when P60 and P61 are in output mode ...

Page 106: ...n chip pull up resistor can be specified in 1 bit units by pull up resistor option register 7 PU7 This port can also be used for key return input Reset signal generation sets port 7 to input mode Figure 4 17 shows a block diagram of port 7 Figure 4 17 Block Diagram of P70 to P75 P70 KR0 to P75 KR5 WRPU RD WRPORT WRPM PU70 to PU75 PM70 to PM75 VDD P ch PU7 PM7 P7 Internal bus Output latch P70 to P7...

Page 107: ...nput and Operational amplifier I O When using P80 ANI8 AMP2 to P83 ANI11 set the registers according to the pin function to be used refer to Tables 4 9 to 4 11 To use P20 ANI0 AMP0 to P27 ANI15 AVREFM and P80 ANI8 AMP2 to P83 ANI11 as a digital input or a digital output it is recommended to select a pin to use starting with the furthest P20 ANI0 AMP0 pin from AVDD Reset signal generation sets P80 ...

Page 108: ...ted 0 Digital output Digital I O selection Output mode 1 Setting prohibited Selects ANI Analog input to be converted 0 Does not select ANI Analog input not to be converted Selects ANI Operational amplifier output to be converted Input mode 1 Does not select ANI Operational amplifier output not to be converted Analog input selection Output mode Setting prohibited Table 4 11 Setting Functions of P83...

Page 109: ...0 PM8 P8 Internal bus Selector Output latch P80 A D converter Operational amplifier input Figure 4 19 Block Diagram of P81 P81 ANI9 AMP2OUT RD WRPORT WRPM PM81 PM8 P8 Internal bus Selector Output latch P81 A D converter Operational amplifier output P8 Port register 8 PM8 Port mode register 8 RD Read signal WR Write signal ...

Page 110: ... RD WRPORT WRPM PM82 PM8 P8 Internal bus Selector Output latch P82 A D converter Operational amplifier input Figure 4 21 Block Diagram of P83 P83 ANI11 RD WRPORT WRPM PM83 PM8 P8 Internal bus Selector A D converter Output latch P83 P8 Port register 8 PM8 Port mode register 8 RD Read signal WR Write signal ...

Page 111: ...X1 X2 or subsystem clock XT1 XT2 or to input an external clock for the main system clock EXCLK the X1 oscillation mode XT1 oscillation mode or external clock input mode must be set by using the clock operation mode select register OSCCTL for details see 5 3 1 Clock operation mode select register OSCCTL The reset value of OSCCTL is 00H all of the P121 to P124 pins are I O port pins At this time set...

Page 112: ...lock Diagram of P120 P120 INTP0 EXLVI WRPU RD WRPORT WRPM PU120 PM120 VDD P ch PU12 PM12 P12 Internal bus Output latch P120 Selector Alternate function P12 Port register 12 PU12 Pull up resistor option register 12 PM12 Port mode register 12 RD Read signal WR Write signal ...

Page 113: ...M12 P12 RD WRPORT WRPM PM121 PM12 P12 EXCLK OSCSEL OSCCTL OSCSEL OSCCTL P121 X1 OCD0A OSCSEL OSCCTL OSCSEL OSCCTL Internal bus Selector Selector Output latch P122 Output latch P121 P12 Port register 12 PU12 Pull up resistor option register 12 PM12 Port mode register 12 OSCCTL Clock operation mode select register RD Read signal WR Write signal ...

Page 114: ...2 P12 RD WRPORT WRPM PM123 PM12 P12 OSCSELS OSCCTL OSCSELS OSCCTL P123 XT1 OSCSELS OSCCTL OSCSELS OSCCTL Internal bus Selector Selector Output latch P124 Output latch P123 P12 Port register 12 PU12 Pull up resistor option register 12 PM12 Port mode register 12 OSCCTL Clock operation mode select register RD Read signal WR Write signal ...

Page 115: ...t the port mode register by referencing 4 5 Settings of Port Mode Register and Output Latch When Using Alternate Function Figure 4 25 Format of Port Mode Register 1 2 1 78K0 KB2 A Symbol 7 6 5 4 3 2 1 0 Address After reset R W PM1 1 1 1 1 PM13 PM12 PM11 PM10 FF21H FFH R W PM2 1 1 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R W PM3 1 1 PM35 1 1 PM32 PM31 1 FF23H FFH R W PM6 1 1 1 1 1 1 PM61 PM60 FF26H ...

Page 116: ...42 PM41 PM40 FF24H FFH R W PM6 1 1 1 1 1 1 PM61 PM60 FF26H FFH R W PM7 1 1 PM75 PM74 PM73 PM72 PM71 PM70 FF27H FFH R W PM8 1 1 1 1 PM83 PM82 PM81 PM80 FF28H FFH R W PM12 1 1 1 PM124 PM123 PM122 PM121 PM120 FF2CH FFH R W PMmn Pmn pin I O mode selection m 0 to 4 6 to 8 12 n 0 to 7 0 Output mode output buffer on 1 Input mode output buffer off Caution Be sure to set bits 3 to 7 of PM0 bits 4 to 7 of P...

Page 117: ...ister 1 2 1 78K0 KB2 A Symbol 7 6 5 4 3 2 1 0 Address After reset R W P1 0 0 0 0 P13 P12 P11 P10 FF01H 00H output latch R W P2 0 0 P25 P24 P23 P22 P21 P20 FF02H 00H output latch R W P3 0 0 P35 0 0 P32 P31 0 FF03H 00H output latch R W P6 0 0 0 0 0 0 P61 P60 FF06H 00H output latch R W P8 0 0 0 0 P83 P82 P81 P80 FF08H 00H output latch R W P12 0 0 0 0 0 P122Note P121Note P120 FF0CH 00H output latch R ...

Page 118: ...0H output latch R W P4 0 0 0 0 0 P42 P41 P40 FF04H 00H output latch R W P6 0 0 0 0 0 0 P61 P60 FF06H 00H output latch R W P7 0 0 P75 P74 P73 P72 P71 P70 FF07H 00H output latch R W P8 0 0 0 0 P83 P82 P81 P80 FF08H 00H output latch R W P12 0 0 0 P124 P123 P122Note P121Note P120 FF0CH 00H output latch R W m 0 to 4 6 to 8 12 n 0 to 7 Pmn Output data control in output mode Input data read in input mode...

Page 119: ...output mode and bits used as alternate function output pins regardless of the settings of these registers These registers can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears these registers to 00H Figure 4 27 Format of Pull up Resistor Option Register 1 2 1 78K0 KB2 A Symbol 7 6 5 4 3 2 1 0 Address After reset R W PU1 0 0 0 0 PU13 PU12 PU11 PU10 FF31H 00H ...

Page 120: ...3CH 00H R W PUmn Pmn pin on chip pull up resistor selection m 0 1 3 4 7 12 n 0 to 5 0 On chip pull up resistor not connected 1 On chip pull up resistor connected 4 A D port configuration register ADPC This register switches the P20 ANI0 AMP0 to P26 ANI6 P80 ANI8 AMP2 to P83 ANI11 and P27 ANI15 AVREFM pins to digital I O of port or analog input of A D converter ADPC can be set by a 1 bit or 8 bit m...

Page 121: ...1 0 0 1 A A A A D D D D D D D D 0 1 0 1 0 A A A D D D D D D D D D 0 1 0 1 1 A A D D D D D D D D D D 0 1 1 1 1 A D D D D D D D D D D D 1 0 0 0 0 D D D D D D D D D D D D Other than above Setting prohibited Note In case of 78K0 KB2 A setting prohibited Cautions 1 Set the channel used for A D conversion to the input mode by using port mode register 2 and 8 PM2 and PM8 2 Do not set the pin that is set ...

Page 122: ...tion is performed on the output latch contents and the result is written to the output latch The output latch contents are output from the pins Once data is written to the output latch it is retained until data is written to the output latch again The data of the output latch is cleared when a reset signal is generated 2 Input mode The pin level is read and an operation is performed on its content...

Page 123: ...0 INTP7 Input 1 P12 TI000 Input 1 TOH1 Output 0 0 TI010 Input 1 TO00 Output 0 0 P13 INTP6 Input 1 ANI0Note 1 Input 1 P20 AMP0 Note 1 Input 1 ANI1Note 1 Input 1 P21 AMP0OUTNote 1 Output 1 ANI2Note 1 Input 1 P22 AMP0 Note 1 Input 1 ANI3Note 1 Input 1 P23 AMP1 Note 1 Input 1 ANI4Note 1 Input 1 P24 AMP1OUTNote 1 Output 1 ANI5Note 1 Input 1 P25 AMP1 Note 1 Input 1 INTP5 Input 1 Input 1 P31 SCK10 Note 2...

Page 124: ... connect an on chip debug emulator QB MINI2 see CHAPTER 26 ON CHIP DEBUG FUNCTION Table 4 12 Settings of Port Mode Register and Output Latch When Using Alternate Function 78K0 KB2 A 2 2 Alternate Function Pin Name Function Name I O PM P SCLA0 I O 0 0 P60 SCK10 Input 1 SDAA0 I O 0 0 P61 SI10 Input 1 ANI8Note 1 Input 1 P80 AMP2 Note 1 Input 1 ANI9Note 1 Input 1 P81 AMP2OUTNote 1 Output 1 ANI10Note 1...

Page 125: ...P1OUTNote 1 Output 1 ANI5Note 1 Input 1 P25 AMP1 Note 1 Input 1 P26 ANI6Note 1 Input 1 ANI15Note 1 Input 1 P27 AVREFM Note 1 Input 1 INTP5 Input 1 Input 1 P31 SCK10 Note 2 Output 0 1 INTP4 Input 1 P32 SI10 Note 2 Input 1 TI51 Input 1 TO51 Output 0 0 P33 INTP3 Input 1 Notes 1 The function can be selected by using the ADPC ADS PM2 OAENn n 0 1 Refer to Tables 4 5 to 4 8 2 The functions of pins whose ...

Page 126: ...1 RTCCL Output 0 0 P40 RTCDIV Output 0 0 P41 RTC1HZ Output 0 0 PCL Output 0 0 SSI10 Input 1 P42 INTP9 Input 1 SCLA0 I O 0 0 P60 SCK10 Input 1 SDAA0 I O 0 0 P61 SI10 Input 1 P70 P75 KR0 KR5 Input 1 ANI8Note Input 1 P80 AMP2 Note Input 1 ANI9Note Input 1 P81 AMP2OUTNote Output 1 ANI10Note Input 1 P82 AMP2 Note Input 1 P83 ANI11Note Input 1 Note The function can be selected by using the ADPC ADS PM8 ...

Page 127: ...the main system clock EXCLK the X1 oscillation mode XT1 oscillation mode or external clock input mode must be set by using the clock operation mode select register OSCCTL for details see 5 3 1 Clock operation mode select register OSCCTL The reset value of OSCCTL is 00H all of the P121 to P124 are I O port pins At this time setting of PM121 to PM124 and P121 to P124 is not necessary Remarks 1 Don t...

Page 128: ...d in the following order in the 78K0 Kx2 A microcontrollers 1 The Pn register is read in 8 bit units 2 The targeted one bit is manipulated 3 The Pn register is written in 8 bit units In step 1 the output latch value 0 of P10 which is an output port is read while the pin statuses of P11 to P13 which are input ports are read If the pin statuses of P11 to P13 are high level at this time the read valu...

Page 129: ...nstruction or using the internal oscillation mode register RCM An external main system clock fEXCLK 1 to 20 MHz can also be supplied from the EXCLK X2 P122 pin An external main system clock input can be disabled by executing the STOP instruction or using RCM As the main system clock a high speed system clock X1 clock or external main system clock or internal high speed oscillation clock can be sel...

Page 130: ...oscillation clock Watchdog timer 8 bit timer H1 when fRL fRL 2 7 or fRL 2 9 is selected Remark fRL Internal low speed oscillation clock frequency 5 2 Configuration of Clock Generator The clock generator includes the following hardware Table 5 1 Configuration of Clock Generator Item Configuration Control registers Clock operation mode select register OSCCTL Processor clock control register PCC Inte...

Page 131: ...15 MOST 14 MOST 13 MOST 11 Oscillation stabilization time counter status register OSTC MCM0 XSEL MCS MSTOP STOP EXCLK OSCSEL AMPH Clock operation mode select register OSCCTL 3 fXP 2 fXP 22 fXP 23 fXP 24 Main clock mode register MCM Main clock mode register MCM Main OSC control register MOC fRH Internal bus Internal bus High speed system clock oscillator Crystal ceramic oscillation External input c...

Page 132: ...rdware clock switch X1 oscillation stabilization time counter OSTS1 OSTS0 OSTS2 Oscillation stabilization time select register OSTS 3 MOST 16 MOST 15 MOST 14 MOST 13 MOST 11 Oscillation stabilization time counter status register OSTC Controller MCM0 XSEL MCS MSTOP EXCLK OSCSEL AMPH Clock operation mode select register OSCCTL 4 fXP 2 fXP 22 fXP 23 fXP 24 Main clock mode register MCM Main clock mode...

Page 133: ...ng Clock Generator The following seven registers are used to control the clock generator Clock operation mode select register OSCCTL Processor clock control register PCC Internal oscillation mode register RCM Main OSC control register MOC Main clock mode register MCM Oscillation stabilization time counter status register OSTC Oscillation stabilization time select register OSTS 1 Clock operation mo...

Page 134: ... the high speed system clock X1 oscillation is selected as the CPU clock supply of the CPU clock is stopped for 4 06 to 16 12 μs after AMPH is set to 1 When the high speed system clock external clock input is selected as the CPU clock supply of the CPU clock is stopped for the duration of 160 external clocks after AMPH is set to 1 4 If the STOP instruction is executed when AMPH 1 supply of the CPU...

Page 135: ... 1 Subsystem clock Note Bit 5 is read only Cautions1 For the 78K0 KB2 A be sure to set bits 3 to 7 to 0 For the 78K0 KC2 A be sure to set bits 3 6 and 7 to 0 2 The peripheral hardware clock fPRS is not divided when the division ratio of the PCC is set 3 The CPU clock fCPU is supplied to the CPU and the A D converter If fCPU is changed therefore the A D converter s conversion clock fAD is also chan...

Page 136: ...lock High Speed System Clock Note 1 Internal High Speed Oscillation Clock Note 1 Subsystem Clock Note 2 CPU Clock fCPU At 10 MHz Operation At 20 MHz Operation At 8 MHz TYP Operation At 32 768 kHz Operation fXP 0 2 μs 0 1 μs 0 25 μs TYP fXP 2 0 4 μs 0 2 μs 0 5 μs TYP fXP 2 2 0 8 μs 0 4 μs 1 0 μs TYP fXP 2 3 1 6 μs 0 8 μs 2 0 μs TYP fXP 2 4 3 2 μs 1 6 μs 4 0 μs TYP fSUB 2 Note 2 122 1 μs Notes 1 The...

Page 137: ...r oscillating 1 Internal low speed oscillator stopped RSTOP Internal high speed oscillator oscillating stopped 0 Internal high speed oscillator oscillating 1 Internal high speed oscillator stopped Notes 1 The value of this register is 00H immediately after a reset release but automatically changes to 80H after internal high speed oscillator has been stabilized 2 Bit 7 is read only Caution When set...

Page 138: ...s enabled 1 X1 oscillator stopped External clock from EXCLK pin is disabled Cautions 1 When setting MSTOP to 1 be sure to confirm that the CPU operates with a clock other than the high speed system clock Specifically set under either of the following conditions 1 78K0 KB2 A When MCS 0 when CPU operates with the internal high speed oscillation clock 2 78K0 KC2 A When MCS 0 when CPU operates with th...

Page 139: ... 0 Operates with internal high speed oscillation clock 1 Operates with high speed system clock Note Bit 1 is read only Cautions 1 XSEL can be changed only once after a reset release 2 Do not rewrite MCM0 when the CPU clock operates with the subsystem clock 3 A clock other than fPRS is supplied to the following peripheral functions regardless of the setting of XSEL and MCM0 Watchdog timer operates ...

Page 140: ...tatus fX 10 MHz fX 20 MHz 1 0 0 0 0 2 11 fX min 204 8 μs min 102 4 μs min 1 1 0 0 0 2 13 fX min 819 2 μs min 409 6 μs min 1 1 1 0 0 2 14 fX min 1 64 ms min 819 2 μs min 1 1 1 1 0 2 15 fX min 3 27 ms min 1 64 ms min 1 1 1 1 1 2 16 fX min 6 55 ms min 3 27 ms min Cautions 1 After the above time has elapsed the bits are set to 1 in order from MOST11 and remain 1 2 The oscillation stabilization time co...

Page 141: ...ction fX 10 MHz fX 20 MHz 0 0 1 2 11 fX 204 8 μs 102 4 μs 0 1 0 2 13 fX 819 2 μs 409 6 μs 0 1 1 2 14 fX 1 64 ms 819 2 μs 1 0 0 2 15 fX 3 27 ms 1 64 ms 1 0 1 2 16 fX 6 55 ms 3 27 ms Other than above Setting prohibited Cautions 1 To set the STOP mode when the X1 clock is used as the CPU clock set OSTS before executing the STOP instruction 2 Do not change the value of the OSTS register during the X1 ...

Page 142: ... X1 oscillator Figure 5 10 Example of External Circuit of X1 Oscillator a Crystal or ceramic oscillation b External clock X1 X2 VSS EXCLK External clock Cautions are listed on the next page 5 4 2 XT1 oscillator The XT1 oscillatorNote oscillates with a crystal resonator standard 32 768 kHz connected to the XT1 and XT2 pins Figure 5 11 shows an example of the external circuit of the XT1 oscillator N...

Page 143: ...t flows Always make the ground point of the oscillator capacitor the same potential as VSS Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator Note that the XT1 oscillator is designed as a low amplitude circuit for reducing power consumption Figure 5 12 shows examples of incorrect resonator connection Figure 5 12 Examples of I...

Page 144: ...scillator potential at points A B and C fluctuates VSS X1 X2 VSS X1 X2 A B C Pmn VDD High current High current e Signals are fetched VSS X1 X2 Remark When using the subsystem clock replace X1 and X2 with XT1 and XT2 respectively Also insert resistors in series on the XT2 side Caution 2 When X2 and XT1 are wired in parallel the crosstalk noise of X2 may increase with XT1 resulting in malfunctioning...

Page 145: ...scillation mode register RCM After a reset release the internal high speed oscillator automatically starts oscillation 8 MHz TYP 5 4 5 Internal low speed oscillator The internal low speed oscillator is incorporated in the 78K0 Kx2 A microcontrollers The internal low speed oscillation clock is only used as the watchdog timer and the clock of 8 bit timer H1 The internal low speed oscillation clock c...

Page 146: ... thus enabling the following 1 Enhancement of security function When the X1 clock is set as the CPU clock by the default setting the device cannot operate if the X1 clock is damaged or badly connected and therefore does not operate after reset is released However the start clock of the CPU is the internal high speed oscillation clock so the device can be started by the internal high speed oscillat...

Page 147: ...oscillation of the X1 or XT1 clock via software see 1 in 5 6 1 Example of controlling high speed system clock and 1 in 5 6 3 Example of controlling subsystem clock 5 When switching the CPU clock to the X1 or XT1 clock wait for the clock oscillation to stabilize and then set switching via software see 3 in 5 6 1 Example of controlling high speed system clock and 2 in 5 6 3 Example of controlling su...

Page 148: ...rocontroller is operating a clock that is not used as the CPU clock can be stopped via software settings The internal high speed oscillation clock and high speed system clock can be stopped by executing the STOP instruction see 4 in 5 6 1 Example of controlling high speed system clock 3 in 5 6 2 Example of controlling internal high speed oscillation clock and 3 in 5 6 3 Example of controlling subs...

Page 149: ...of oscillation of the X1 or XT1 clock via software see 1 in 5 6 1 Example of controlling high speed system clock and 1 in 5 6 3 Example of controlling subsystem clock 5 When switching the CPU clock to the X1 or XT1 clock wait for the clock oscillation to stabilize and then set switching via software see 3 in 5 6 1 Example of controlling high speed system clock and 2 in 5 6 3 Example of controlling...

Page 150: ...es for the following cases 1 When oscillating X1 clock 2 When using external main system clock 3 When using high speed system clock as CPU clock and peripheral hardware clock 4 When stopping high speed system clock 1 Example of setting procedure when oscillating the X1 clock 1 Setting frequency OSCCTL register Using AMPH set the gain of the on chip oscillator according to the frequency to be used ...

Page 151: ...ral functions after a reset release The value of AMPH can be changed only once after a reset release The clock supply to the CPU is stopped for the duration of 160 external clocks after AMPH is set to 1 Remark fXH High speed system clock oscillation frequency 2 Setting P121 X1 and P122 X2 EXCLK pins and selecting operation mode OSCCTL register When EXCLK and OSCSEL are set to 1 the mode is switche...

Page 152: ...ecting the division ratio PCC register When CSS is cleared to 0 the main system clock is supplied to the CPU To select the CPU clock division ratio use PCC0 PCC1 and PCC2 CSS PCC2 PCC1 PCC0 CPU Clock fCPU Selection 0 0 0 fXP 0 0 1 fXP 2 default 0 1 0 fXP 2 2 0 1 1 fXP 2 3 1 0 0 fXP 2 4 0 Other than above Setting prohibited 4 Example of setting procedure when stopping the high speed system clock Th...

Page 153: ...tion clock 0 1 High speed system clock 1 Subsystem clock 2 Stopping the high speed system clock MOC register When MSTOP is set to 1 X1 oscillation is stopped the input of the external clock is disabled Caution Be sure to confirm that MCS 0 or CLS 1 when setting MSTOP to 1 In addition stop peripheral hardware that is operating on the high speed system clock 5 6 2 Example of controlling internal hig...

Page 154: ...rocedure when restarting oscillation of the internal high speed oscillation clock Oscillating the high speed system clockNote This setting is required when using the high speed system clock as the peripheral hardware clock See 5 6 1 1 Example of setting procedure when oscillating the X1 clock and 2 Example of setting procedure when using the external main system clock Note The setting of 1 is not ...

Page 155: ... that RSTS is 1 3 Executing the STOP instruction When the STOP instruction is executed the system is placed in the STOP mode and internal high speed oscillation clock is stopped b To stop internal high speed oscillation clock by setting RSTOP to 1 1 Confirming the CPU clock status PCC and MCM registers Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high speed...

Page 156: ...e following cases 1 When oscillating XT1 clock 2 When using subsystem clock as CPU clock 3 When stopping subsystem clock 1 Example of setting procedure when oscillating the XT1 clock 1 Setting XT1 and XT2 pins and selecting operation mode OSCCTL register When OSCSELS is set to 1 the mode is switched from port mode to XT1 oscillation mode 2 Waiting for the stabilization of the subsystem clock oscil...

Page 157: ...hange the CPU clock to a clock other than the subsystem clock CLS MCS CPU Clock Status 0 0 Internal high speed oscillation clock 0 1 High speed system clock 1 Subsystem clock 2 Stopping the subsystem clock OSCCTL register When OSCSELS is cleared to 0 XT1 oscillation is stopped Cautions1 Be sure to confirm that CLS 0 when clearing OSCSELS to 0 In addition stop the real time counter and clock output...

Page 158: ...omatically starts oscillation after a reset release and the watchdog timer is driven 240 kHz TYP if the watchdog timer operation has been enabled by the option byte 1 Example of setting procedure when stopping the internal low speed oscillation clock 1 Setting LSRSTOP to 1 RCM register When LSRSTOP is set to 1 the internal low speed oscillation clock is stopped 2 Example of setting procedure when ...

Page 159: ...r MCM CSS Bit 4 of processor clock control register PCC MCM0 Bit 0 of MCM EXCLK Bit 7 of the clock operation mode select register OSCCTL don t care Table 5 4 Clocks Supplied to CPU and Peripheral Hardware and Register Setting 78K0 KC2 A Supplied Clock Clock Supplied to CPU Clock Supplied to Peripheral Hardware XSEL CSS MCM0 EXCLK Internal high speed oscillation clock 0 0 X1 clock 1 0 0 0 Internal ...

Page 160: ...lation Internal low speed oscillation Operable Internal high speed oscillation Operating X1 oscillation EXCLK input Selectable by CPU Internal low speed oscillation Operable Internal high speed oscillation Selectable by CPU X1 oscillation EXCLK input Operating Internal low speed oscillation Operable Internal high speed oscillation Stops X1 oscillation EXCLK input Stops Internal low speed oscillati...

Page 161: ...illation EXCLK input Operable XT1 oscillation Operable CPU Operating with X1 oscillation or EXCLK input CPU X1 oscillation EXCLK input STOP CPU X1 oscillation EXCLK input HALT Internal low speed oscillation Operable Internal high speed oscillation Selectable by CPU X1 oscillation EXCLK input Operating XT1 oscillation Selectable by CPU Internal low speed oscillation Operable Internal high speed osc...

Page 162: ... Must not be checked 1 1 A B C X1 clock 10 MHz fXH 20 MHz 1 0 1 0 Must be checked 1 1 A B C external main clock 10 MHz fXH 20 MHz 1 1 1 0 Must not be checked 1 1 Caution Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used see CHAPTER 28 ELECTRICAL SPECIFICATIONS 3 CPU operating with subsystem clock D after reset release A Note The CPU operates with th...

Page 163: ...f this flag can be changed only once after a reset release This setting is not necessary if it has already been set Caution Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used see CHAPTER 28 ELECTRICAL SPECIFICATIONS 5 CPU clock changing from internal high speed oscillation clock B to subsystem clock D Note Note The 78K0 KB2 A is not provided with a s...

Page 164: ...Transition OSCSELS Waiting for Oscillation Stabilization CSS C D 1 Necessary 1 Unnecessary if the CPU is operating with the subsystem clock 8 CPU clock changing from subsystem clock D to internal high speed oscillation clock B Note The 78K0 KB2 A is not provided with a subsystem clock Setting sequence of SFR registers Setting Flag of SFR Register Status Transition RSTOP RSTS MCM0 CSS D B 0 Confirm...

Page 165: ...necessary if this register is already set Note The value of this flag can be changed only once after a reset release This setting is not necessary if it has already been set Caution Set the X1 clock after the supply voltage has reached the operable voltage of the clock to be used see CHAPTER 28 ELECTRICAL SPECIFICATIONS 10 HALT mode E set while CPU is operating with internal high speed oscillation...

Page 166: ...CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below Table 5 6 Changing CPU Clock 1 2 1 78K0 KB2 A CPU Clock Before Change After Change Condition Before Change Processing After Change X1 clock Stabilization of X1 oscillation MSTOP 0 OSCSEL 1 EXCLK 0 After elapse of oscillation stabilization time Internal high speed oscillator can be stopped ...

Page 167: ...n clock Operating current can be reduced by stopping internal high speed oscillator RSTOP 1 X1 clock X1 oscillation can be stopped MSTOP 1 External main system clock XT1 clock Stabilization of XT1 oscillation OSCSELS 1 After elapse of oscillation stabilization time External main system clock input can be disabled MSTOP 1 Internal high speed oscillation clock Oscillation of internal high speed osci...

Page 168: ...1 1 2 clocks 2 clocks 2 clocks 2 clocks 1 0 0 1 clock 1 clock 1 clock 1 clock Remark The number of clocks listed in Table 5 7 is the number of CPU clocks before switchover Table 5 8 Time Required for Switchover of CPU Clock and Main System Clock Cycle Division Factor 78K0 KC2 A Set Value Before Switchover Set Value After Switchover CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 ...

Page 169: ...ng on the internal high speed oscillation clock or the high speed system clock can be ascertained using bit 1 MCS of MCM Table 5 9 Maximum Time Required for Main System Clock Switchover Set Value Before Switchover Set Value After Switchover MCM0 MCM0 0 1 0 1 2fRH fXH clock 1 1 2fXH fRH clock Cautions 1 When switching the internal high speed oscillation clock to the high speed system clock bit 2 XS...

Page 170: ...PU is operating on the high speed system clock RSTOP 1 X1 clock External main system clock MCS 0 The CPU is operating on the internal high speed oscillation clock MSTOP 1 Table 5 11 Conditions Before the Clock Oscillation Is Stopped and Flag Settings 78K0 KC2 A Clock Conditions Before Clock Oscillation Is Stopped External Clock Input Disabled Flag Settings of SFR Register Internal high speed oscil...

Page 171: ... counter 00 N Y N N N Y TI000 pin Note 2 50 N Y N N N Y TI50 pin Note 2 8 bit timer event counter 51 N Y N N N Y TI51 pin Note 2 H0 N Y N N Y N 8 bit timer H1 N Y N Y N N Real time counter N N Y N N N Watchdog timer N N N Y N N Clock output N Y Y N N N A D converter Y N N N N N Operational amplifier N Y N N N N UART6 N Y N N Y N CSI10 N Y N N N Y SCK10 pin Note 2 Serial interface IICA N Y N N N Y ...

Page 172: ... output 16 bit timer event counter 00 can output a square wave with any selected frequency 3 External event counter 16 bit timer event counter 00 can measure the number of pulses of an externally input signal 4 One shot pulse output 16 bit timer event counter 00 can output a one shot pulse whose output pulse width can be set freely 5 PPG output 16 bit timer event counter 00 can output a rectangula...

Page 173: ...imer input TI000 TI010 pins Note Timer output TO00 pin Note output controller Control registers 16 bit timer mode control register 00 TMC00 Capture compare control register 00 CRC00 16 bit timer output control register 00 TOC00 Prescaler mode register 00 PRM00 Input switch control register ISC Port mode register 0 1 PM0 PM1 Note Port register 0 1 P0 P1 Note Note The port pins with which the I O pi...

Page 174: ... A TI000 TOH0 INTP7 P12 TI010 TO00 TOH1 INTP6 P13 output latch P13 PM13 78K0 KB2 A TI000 P00 TI010 TO00 P01 output latch P01 PM01 Cautions 1 In case of 78K0 KB2 A The valid edge of TI010 and timer output TO00 cannot be used for the P13 pin at the same time Select either of the functions 2 In case of 78K0 KC2 A The valid edge of TI010 and timer output TO00 cannot be used for the P01 pin at the same...

Page 175: ...s when inputting the valid edge to the TI000 pin If TM00 and CR000 match in the mode in which the clear start occurs when TM00 and CR000 match OSPT00 is set to 1 in one shot pulse output mode or the valid edge is input to the TI000 pin Caution Even if TM00 is read the value is not captured by CR010 2 16 bit timer capture compare register 000 CR000 16 bit timer capture compare register 010 CR010 CR...

Page 176: ...pture trigger is input As the capture trigger an edge of a phase reverse to that of the TI000 pin or the valid edge of the TI010 pin can be selected by using CRC00 or PRM00 Figure 6 4 Format of 16 Bit Timer Capture Compare Register 010 CR010 CR010 FF15H FF14H Address FF14H FF15H After reset 0000H R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i When CR010 is used as a compare register The value set in ...

Page 177: ...match interrupt immediately after the timer operation does not occur and timer output is not changed and the first match timing is as follows A match interrupt occurs at the timing when the timer counter TM00 register is changed from 0000H to 0001H When the timer counter is cleared due to overflow When the timer counter is cleared due to TI000 pin valid edge when clear start mode is entered by TI0...

Page 178: ... ES000 Position of edge to be captured 01 Rising 00 Falling TI000 pin input Note 11 Both edges Capture operation of CR010 Interrupt signal INTTM010 signal is generated each time value is captured Note The capture operation of CR010 is not affected by the setting of the CRC001 bit Caution To capture the count value of the TM00 register to the CR000 register by using the phase reverse to that input ...

Page 179: ...ows 78K0 KB2 A Shared with the pins of port 1 78K0 KC2 A Shared with the pins of port 0 1 16 bit timer mode control register 00 TMC00 TMC00 is an 8 bit register that sets the 16 bit timer event counter 00 operation mode TM00 clear mode and output timing and detects an overflow Rewriting TMC00 is prohibited during operation when TMC003 and TMC002 other than 00 However it can be changed when TMC003 ...

Page 180: ...ntered upon a match between TM00 and CR000 TMC001 Condition to reverse timer output TO00 0 Match between TM00 and CR000 or match between TM00 and CR010 1 Match between TM00 and CR000 or match between TM00 and CR010 Trigger input of TI000 pin valid edge OVF00 TM00 overflow flag Clear 0 Clears OVF00 to 0 or TMC003 and TMC002 00 Set 1 Overflow occurs OVF00 is set to 1 when the value of TM00 changes f...

Page 181: ...apture trigger selection 0 Captures on valid edge of TI010 pin 1 Captures on valid edge of TI000 pin by reverse phase Note The valid edge of the TI010 and TI000 pin is set by PRM00 If ES001 and ES000 are set to 11 both edges when CRC001 is 1 the valid edge of the TI000 pin cannot be detected CRC000 CR000 operating mode selection 0 Operates as compare register 1 Operates as capture register If TMC0...

Page 182: ...ut TOC00 can be rewritten while only OSPT00 is operating when TMC003 and TMC002 other than 00 Rewriting the other bits is prohibited during operation However TOC004 can be rewritten during timer operation as a means to rewrite CR010 see 6 5 1 Rewriting CR010 during TM00 operation TOC00 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears TOC00 to 00H Cautio...

Page 183: ... of TO00 output status 0 0 No change 0 1 Initial value of TO00 output is low level TO00 output is cleared to 0 1 0 Initial value of TO00 output is high level TO00 output is set to 1 1 1 Setting prohibited LVS00 and LVR00 can be used to set the initial value of the TO00 output level If the initial value does not have to be set leave LVS00 and LVR00 as 00 Be sure to set LVS00 and LVR00 when TOE00 1 ...

Page 184: ...alid edge Setting the TI000 pin as a capture trigger 2 If the operation of the 16 bit timer event counter 00 is enabled when the TI000 or TI010 pin is at high level and when the valid edge of the TI000 or TI010 pin is specified to be the rising edge or both edges the high level of the TI000 or TI010 pin is detected as a rising edge Note this when the TI000 or TI010 pin is pulled up However the ris...

Page 185: ...4 5 Notes 1 The frequency that can be used for the peripheral hardware clock fPRS differs depending on the power supply voltage Power supply voltage Use frequency range of peripheral hardware clock fPRS 2 7 V VDD 5 5 V fPRS 20 MHz 1 8 V VDD 2 7 V fPRS 5 MHz The values shown in the table above are those when fPRS fXH XSEL 1 2 If the peripheral hardware clock fPRS operates on the internal high speed...

Page 186: ...tput latches of P12 and P13 may be 0 or 1 Figure 6 10 Format of Port Mode Register 1 PM1 Address FF21H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PIM1 1 1 1 1 PM13 PM12 PM11 PM10 PIM1n P1n pin I O mode selection n 0 to 3 0 Output mode output buffer on 1 Input mode output buffer off 78K0 KC2 A When using the P01 TO00 TI010 pin for timer output set PM01 and the output latches of P01 to 0 When using ...

Page 187: ... match interrupt signal INTTM000 is generated This INTTM000 signal enables TM00 to operate as an interval timer Remarks 1 For the setting of I O pins see 6 3 5 Port mode registers 0 1 PM0 PM1 2 For how to enable the INTTM000 interrupt see CHAPTER 18 INTERRUPT FUNCTIONS Figure 6 12 Block Diagram of Interval Timer Operation 16 bit counter TM00 CR000 register Operable bits TMC003 TMC002 Count clock C...

Page 188: ... OSPT00 TOC001 TOE00 0 0 0 d Prescaler mode register 00 PRM00 0 0 0 0 0 3 2 PRM001 PRM000 ES101 ES100 ES001 ES000 Selects count clock 0 0 1 0 1 e 16 bit timer counter 00 TM00 By reading TM00 the count value can be read f 16 bit capture compare register 000 CR000 If M is set to CR000 the interval time is as follows Interval time M 1 Count clock cycle Setting CR000 to 0000H is prohibited g 16 bit ca...

Page 189: ...11 00 N N N 1 2 TMC003 TMC002 bits 11 TMC003 TMC002 bits 00 Register initial setting PRM00 register CRC00 register CR000 register port setting Initial setting of these registers is performed before setting the TMC003 and TMC002 bits to 11 Starts count operation The counter is initialized and counting is stopped by clearing the TMC003 and TMC002 bits to 00 START STOP 1 Count operation start flow 2 ...

Page 190: ...ignal INTTM000 is generated and TO00 output is inverted This TO00 output that is inverted at fixed intervals enables TO00 to output a square wave Remarks 1 For the setting of I O pins see 6 3 5 Port mode registers 0 and 1 PM0 PM1 2 For how to enable the INTTM000 signal interrupt see CHAPTER 18 INTERRUPT FUNCTIONS Figure 6 16 Block Diagram of Square Wave Output Operation 16 bit counter TM00 CR000 r...

Page 191: ...match between TM00 and CR000 0 1 1 1 Specifies initial value of TO00 output F F d Prescaler mode register 00 PRM00 0 0 0 0 0 3 2 PRM001 PRM000 ES101 ES100 ES001 ES000 Selects count clock 0 0 1 0 1 e 16 bit timer counter 00 TM00 By reading TM00 the count value can be read f 16 bit capture compare register 000 CR000 If M is set to CR000 the interval time is as follows Square wave frequency 1 2 M 1 C...

Page 192: ...Register initial setting PRM00 register CRC00 register TOC00 registerNote CR000 register port setting Initial setting of these registers is performed before setting the TMC003 and TMC002 bits to 11 Starts count operation The counter is initialized and counting is stopped by clearing the TMC003 and TMC002 bits to 00 START STOP 1 Count operation start flow 2 Count operation stop flow N 11 00 N N N 1...

Page 193: ...l second time or later Number of times of detection of valid edge of external event Set value of CR000 1 However the first match interrupt immediately after the timer event counter has started operating is generated with the following timing Timing of generation of INTTM000 signal first time only Number of times of detection of valid edge of external event input Set value of CR000 2 To detect the ...

Page 194: ...00 0 0 0 0 1 0 1 LVR00 LVS00 TOC004 OSPE00 OSPT00 TOC001 TOE00 0 1 0 1 0 1 0 Disables TO00 output 1 Enables TO00 output 00 Does not invert TO00 output on match between TM00 and CR000 CR010 01 Inverts TO00 output on match between TM00 and CR000 10 Inverts TO00 output on match between TM00 and CR010 11 Inverts TO00 output on match between TM00 and CR000 CR010 Specifies initial value of TO00 output F...

Page 195: ...ter 000 CR000 If M is set to CR000 the interrupt signal INTTM000 is generated when the number of external events reaches M 1 Setting CR000 to 0000H is prohibited g 16 bit capture compare register 010 CR010 Usually CR010 is not used in the external event counter mode However a compare match interrupt INTTM010 is generated when the set value of CR010 matches the value of TM00 Therefore mask the inte...

Page 196: ...ter port setting START STOP 1 2 Compare match interrupt INTTM000 Compare register CR000 TO00 output control bits TOC004 TOC001 TOE00 TO00 output N 00 Initial setting of these registers is performed before setting the TMC003 and TMC002 bits to 11 Starts count operation The counter is initialized and counting is stopped by clearing the TMC003 and TMC002 bits to 00 1 Count operation start flow 2 Coun...

Page 197: ...are used as compare registers and capture registers a When CR000 and CR010 are used as compare registers Signals INTTM000 and INTTM010 are generated when the value of TM00 matches the value of CR000 and CR010 b When CR000 and CR010 are used as capture registers The count value of TM00 is captured to CR000 and the INTTM000 signal is generated when the valid edge is input to the TI010 pin or when th...

Page 198: ...ter Figure 6 23 Block Diagram of Clear Start Mode Entered by TI000 Pin Valid Edge Input CR000 Compare Register CR010 Compare Register Timer counter TM00 Clear Output controller Edge detection Compare register CR010 Match signal TO00 pin Match signal Interrupt signal INTTM000 Interrupt signal INTTM010 TI000 pin Compare register CR000 Operable bits TMC003 TMC002 Count clock TO00 output ...

Page 199: ...TTM010 TO00 output M 10 M N N N N M M M 00 N b TOC00 13H PRM00 10H CRC00 00H TMC00 0AH TM00 register 0000H Operable bits TMC003 TMC002 Count clear input TI000 pin input Compare register CR000 Compare match interrupt INTTM000 Compare register CR010 Compare match interrupt INTTM010 TO00 output M 10 M N N N N M M M 00 N a and b differ as follows depending on the setting of bit 1 TMC001 of the 16 bit ...

Page 200: ...Timing Example of Clear Start Mode Entered by TI000 Pin Valid Edge Input CR000 Compare Register CR010 Capture Register 1 2 a TOC00 13H PRM00 10H CRC00 04H TMC00 08H CR000 0001H TM00 register 0000H Operable bits TMC003 TMC002 Capture count clear input TI000 pin input Compare register CR000 Compare match interrupt INTTM000 Capture register CR010 Capture interrupt INTTM010 TO00 output 0001H 10 Q P N ...

Page 201: ...ster CR010 Capture interrupt INTTM010 TO00 output 0003H 0003H 10 Q P N M S 00 0000H M 4 4 4 4 N S P Q This is an application example where the width set to CR000 4 clocks in this example is to be output from the TO00 pin when the count value has been captured cleared The count value is captured to CR010 a capture interrupt signal INTTM010 is generated TM00 is cleared to 0000H and the TO00 output i...

Page 202: ...er Figure 6 27 Block Diagram of Clear Start Mode Entered by TI000 Pin Valid Edge Input CR000 Capture Register CR010 Compare Register Timer counter TM00 Clear Output controller Edge detection Capture register CR000 Capture signal TO00 pin Match signal Interrupt signal INTTM010 Interrupt signal INTTM000 TI000 pin Compare register CR010 Operable bits TMC003 TMC002 Count clock TO00 output ...

Page 203: ...P N M S 00 L 0001H 0000H M N S P This is an application example where the TO00 output level is to be inverted when the count value has been captured cleared TM00 is cleared at the rising edge detection of the TI000 pin and it is captured to CR000 at the falling edge detection of the TI000 pin When bit 1 CRC001 of capture compare control register 00 CRC00 is set to 1 the count value of TM00 is capt...

Page 204: ...this example is to be output from the TO00 pin when the count value has been captured cleared TM00 is cleared to 0000H at the rising edge detection of the TI000 pin and captured to CR000 at the falling edge detection of the TI000 pin The TO00 output is inverted when TM00 is cleared to 0000H because the rising edge of the TI000 pin has been detected or when the value of TM00 matches that of a compa...

Page 205: ...r output TO00 cannot be used when detecting the valid edge of the TI010 pin is used Figure 6 30 Timing Example of Clear Start Mode Entered by TI000 Pin Valid Edge Input CR000 Capture Register CR010 Capture Register 1 3 a TOC00 13H PRM00 30H CRC00 05H TMC00 0AH TM00 register 0000H Operable bits TMC003 TMC002 Capture count clear input TI000 pin input Capture register CR000 Capture interrupt INTTM000...

Page 206: ...er 0000H Operable bits TMC003 TMC002 Capture trigger input TI010 pin input Capture register CR000 Capture interrupt INTTM000 Capture count clear input TI000 Capture register CR010 Capture interrupt INTTM010 10 R S T O L M N P Q 00 FFFFH L L 0000H 0000H L M N O P Q R S T This is a timing example where an edge is not input to the TI000 pin in an application where the count value is captured to CR000...

Page 207: ...d to CR000 in the phase reverse to the falling edge of the TI000 pin i e rising edge and to CR010 at the falling edge of the TI000 pin The high and low level widths of the input pulse can be calculated by the following expressions High level width CR010 value CR000 value Count clock cycle Low level width CR000 value Count clock cycle If the reverse phase of the TI000 pin is selected as a trigger t...

Page 208: ...egister 1 CR000 used as capture register 0 CR010 used as compare register 1 CR010 used as capture register 0 TI010 pin is used as capture trigger of CR000 1 Reverse phase of TI000 pin is used as capture trigger of CR000 c 16 bit timer output control register 00 TOC00 0 0 0 0 1 0 1 LVR00 LVS00 TOC004 OSPE00 OSPT00 TOC001 TOE00 0 Disables TO00 outputNote 1 Enables TO00 output 00 Does not invert TO00...

Page 209: ...egister is used as a compare register and when its value matches the count value of TM00 an interrupt signal INTTM000 is generated The count value of TM00 is not cleared To use this register as a capture register select either the TI000 or TI010 pinNote input as a capture trigger When the valid edge of the capture trigger is detected the count value of TM00 is stored in CR000 Note The timer output...

Page 210: ... Register initial setting PRM00 register CRC00 register TOC00 registerNote CR000 CR010 registers TMC00 TMC001 bit port setting Initial setting of these registers is performed before setting the TMC003 and TMC002 bits to 10 Starts count operation When the valid edge is input to the TI000 pin the value of the TM00 register is cleared START 1 Count operation start flow 2 TM00 register clear start flo...

Page 211: ... available Both CR000 and CR010 are used as compare registers One of CR000 or CR010 is used as a compare register and the other is used as a capture register Both CR000 and CR010 are used as capture registers Remarks 1 For the setting of the I O pins see 6 3 5 Port mode registers 0 and 1 PM0 PM1 2 For how to enable the INTTM000 signal interrupt see CHAPTER 18 INTERRUPT FUNCTIONS 1 Free running tim...

Page 212: ...n example where two compare registers are used in the free running timer mode The TO00 output level is reversed each time the count value of TM00 matches the set value of CR000 or CR010 When the count value matches the register value the INTTM000 or INTTM010 signal is generated 2 Free running timer mode operation CR000 compare register CR010 capture register Figure 6 35 Block Diagram of Free Runni...

Page 213: ...rrupt INTTM010 TO00 output Overflow flag OVF00 0 write clear 0 write clear 0 write clear 0 write clear 01 M N S P Q 00 0000H 0000H M N S P Q This is an application example where a compare register and a capture register are used at the same time in the free running timer mode In this example the INTTM000 signal is generated and the TO00 output is reversed each time the count value of TM00 matches ...

Page 214: ...000 Capture signal Capture signal Interrupt signal INTTM010 Interrupt signal INTTM000 Capture register CR010 Operable bits TMC003 TMC002 Count clock Edge detection TI000 pin Edge detection TI010 pin Selector Remark If both CR000 and CR010 are used as capture registers in the free running timer mode the TO00 output level is not inverted However it can be inverted each time the valid edge of the TI0...

Page 215: ...ger input TI010 Capture register CR000 Capture interrupt INTTM000 Overflow flag OVF00 01 M A B C D E N S P Q 00 0 write clear 0 write clear 0 write clear 0 write clear 0000H A B C D E 0000H M N S P Q This is an application example where the count values that have been captured at the valid edges of separate capture trigger signals are stored in separate capture registers in the free running timer ...

Page 216: ...apture register CR000 Capture interrupt INTTM000 Capture trigger input TI000 Capture register CR010 Capture interrupt INTTM010 01 L M P S N O R Q T 00 0000H 0000H L M N O P Q R S T L L This is an application example where both the edges of the TI010 pin are detected and the count value is captured to CR000 in the free running timer mode When both CR000 and CR010 are used as capture registers and w...

Page 217: ...0 0 CR000 used as compare register 1 CR000 used as capture register 0 CR010 used as compare register 1 CR010 used as capture register 0 TI010 pin is used as capture trigger of CR000 1 Reverse phase of TI000 pin is used as capture trigger of CR000 c 16 bit timer output control register 00 TOC00 0 0 0 0 1 0 1 LVR00 LVS00 TOC004 OSPE00 OSPT00 TOC001 TOE00 0 Disables TO00 output 1 Enables TO00 output ...

Page 218: ...ompare register 000 CR000 When this register is used as a compare register and when its value matches the count value of TM00 an interrupt signal INTTM000 is generated The count value of TM00 is not cleared To use this register as a capture register select either the TI000 or TI010 pin input as a capture trigger When the valid edge of the capture trigger is detected the count value of TM00 is stor...

Page 219: ... M 00 1 2 00 N TMC003 TMC002 bits 0 1 Register initial setting PRM00 register CRC00 register TOC00 registerNote CR000 CR010 register TMC00 TMC001 bit port setting Initial setting of these registers is performed before setting the TMC003 and TMC002 bits to 01 Starts count operation START 1 Count operation start flow TMC003 TMC002 bits 0 0 The counter is initialized and counting is stopped by cleari...

Page 220: ...G output are as follows Pulse cycle Set value of CR000 1 Count clock cycle Duty Set value of CR010 1 Set value of CR000 1 Caution To change the duty factor value of CR010 during operation see 6 5 1 Rewriting CR010 during TM00 operation Remarks 1 For the setting of I O pins see 6 3 5 Port mode registers 0 and 1 PM0 PM1 2 For how to enable the INTTM000 signal interrupt see CHAPTER 18 INTERRUPT FUNCT...

Page 221: ... between TM00 and CR000 CR010 00 Disables one shot pulse output Specifies initial value of TO00 output F F 0 1 1 1 d Prescaler mode register 00 PRM00 0 0 0 0 0 3 2 PRM001 PRM000 ES110 ES100 ES010 ES000 Selects count clock 0 0 1 0 1 e 16 bit timer counter 00 TM00 By reading TM00 the count value can be read f 16 bit capture compare register 000 CR000 An interrupt signal INTTM000 is generated when th...

Page 222: ...s 11 Register initial setting PRM00 register CRC00 register TOC00 registerNote CR000 CR010 registers port setting Initial setting of these registers is performed before setting the TMC003 and TMC002 bits Starts count operation START 1 Count operation start flow TMC003 TMC002 bits 00 The counter is initialized and counting is stopped by clearing the TMC003 and TMC002 bits to 00 STOP 2 Count operati...

Page 223: ... OSPT00 to 1 or detecting the valid edge of the TI000 pin while the one shot pulse is output To output the one shot pulse again generate the trigger after the current one shot pulse output has completed 2 To use only the setting of OSPT00 to 1 as the trigger of one shot pulse output do not change the level of the TI000 pin or its alternate function port pin Otherwise the pulse will be unexpectedly...

Page 224: ...0 0 0 0 CRC002 CRC001 CRC000 CR000 used as compare register CR010 used as compare register c 16 bit timer output control register 00 TOC00 0 0 1 1 1 0 1 LVR00 LVS00 TOC004 OSPE00 OSPT00 TOC001 TOE00 Enables TO00 output Inverts TO00 output on match between TM00 and CR000 CR010 Specifies initial value of TO00 output Enables one shot pulse output Software trigger is generated by writing 1 to this bit...

Page 225: ...r is used as a compare register when a one shot pulse is output When the value of TM00 matches that of CR000 an interrupt signal INTTM000 is generated and the TO00 output level is inverted g 16 bit capture compare register 010 CR010 This register is used as a compare register when a one shot pulse is output When the value of TM00 matches that of CR010 an interrupt signal INTTM010 is generated and ...

Page 226: ...nput TI000 pin Overflow plug OVF00 Compare register CR000 Compare match interrupt INTTM000 Compare register CR010 Compare match interrupt INTTM010 TO00 output TO00 output control bits TOE00 TOC004 TOC001 N M N M N M 01 or 10 00 00 N N N M M M M 1 M 1 1 2 2 3 TO00 output level is not inverted because no one shot trigger is input Time from when the one shot pulse trigger is input until the one shot ...

Page 227: ...gisters is performed before setting the TMC003 and TMC002 bits Starts count operation START 1 Count operation start flow 2 One shot trigger input flow TMC003 TMC002 bits 00 The counter is initialized and counting is stopped by clearing the TMC003 and TMC002 bits to 00 STOP 3 Count operation stop flow TOC00 OSPT00 bit 1 or edge input to TI000 pin Write the same value to the bits other than the OSPT...

Page 228: ...rol register 00 TMC00 If it is set to 1 clear it to 0 by software Figure 6 47 Block Diagram of Pulse Width Measurement Free Running Timer Mode Timer counter TM00 Capture register CR000 Capture signal Capture signal Interrupt signal INTTM010 Interrupt signal INTTM000 Capture register CR010 Operable bits TMC003 TMC002 Count clock Edge detection TI000 pin Edge detection TI010 pin Selector Figure 6 48...

Page 229: ...tected the count value of TM00 is captured to CR000 Specify detection of both the edges of the TI000 and TI010 pins By this measurement method the previous count value is subtracted from the count value captured by the edge of each input signal Therefore save the previously captured value to a separate register in advance If an overflow occurs the value becomes negative if the previously captured ...

Page 230: ... of another a high level width low level width and cycle are calculated If an overflow occurs the value becomes negative if one captured value is simply subtracted from another and therefore a borrow occurs bit 0 CY of the program status word PSW is set to 1 If this happens ignore CY and take the calculated value as the pulse width In addition clear bit 0 OVF00 of 16 bit timer mode control registe...

Page 231: ...s from adding 10000H to the value stored in CR010 as a cycle Clear bit 0 OVF00 of 16 bit timer mode control register 00 TMC00 to 0 Figure 6 51 Timing Example of Pulse Width Measurement 3 TMC00 08H PRM00 10H CRC00 07H FFFFH TM00 register 0000H Operable bits TMC003 TMC002 Capture count clear input TI000 Capture register CR000 Capture register CR010 Capture interrupt INTTM010 Overflow flag OVF00 Capt...

Page 232: ...10 used as capture register 0 TI010 pin is used as capture trigger of CR000 1 Reverse phase of TI000 pin is used as capture trigger of CR000 c 16 bit timer output control register 00 TOC00 0 0 0 0 0 LVR00 LVS00 TOC004 OSPE00 OSPT00 TOC001 TOE00 0 0 0 d Prescaler mode register 00 PRM00 0 1 0 1 0 1 0 1 0 3 2 PRM001 PRM000 ES110 ES100 ES010 ES000 Selects count clock setting valid edge of TI000 is pro...

Page 233: ...ter 000 CR000 This register is used as a capture register Either the TI000 or TI010 pin is selected as a capture trigger When a specified edge of the capture trigger is detected the count value of TM00 is stored in CR000 g 16 bit capture compare register 010 CR010 This register is used as a capture register The signal input to the TI000 pin is used as a capture trigger When the capture trigger is ...

Page 234: ...gger input TI010 Capture register CR000 Capture interrupt INTTM000 01 D00 D00 D01 D01 D02 D02 D03 D03 D04 D04 D10 D10 D11 D11 D12 D12 D13 D13 00 00 0000H 0000H 1 2 2 2 2 2 2 2 2 2 3 b Example of clear start mode entered by TI000 pin valid edge FFFFH TM00 register 0000H Operable bits TMC003 TMC002 Capture count clear input TI000 Capture register CR000 Capture interrupt INTTM000 Capture register CR0...

Page 235: ...TMC002 bits 01 or 10 Register initial setting PRM00 register CRC00 register port setting Initial setting of these registers is performed before setting the TMC003 and TMC002 bits Starts count operation START 1 Count operation start flow TMC003 TMC002 bits 00 The counter is initialized and counting is stopped by clearing the TMC003 and TMC002 bits to 00 STOP 3 Count operation stop flow Note The cap...

Page 236: ...peration may be performed Procedure for changing value of CR010 1 Disable interrupt INTTM010 TMMK010 1 2 Disable reversal of the timer output when the value of TM00 matches that of CR010 TOC004 0 3 Change the value of CR010 4 Wait for one cycle of the count clock of TM00 5 Enable reversal of the timer output when the value of TM00 matches that of CR010 TOC004 1 6 Clear the interrupt flag of INTTM0...

Page 237: ...55 Timing Example of LVR00 and LVS00 TOC00 LVS00 bit TOC00 LVR00 bit Operable bits TMC003 TMC002 TO00 output INTTM000 signal 1 00 2 1 3 4 4 4 01 10 or 11 1 The TO00 output goes high when LVS00 and LVR00 10 2 The TO00 output goes low when LVS00 and LVR00 01 the pin output remains unchanged from the high level even if LVS00 and LVR00 are cleared to 00 3 The timer starts operating when TMC003 and TMC...

Page 238: ...C00 00H As free running timer As PPG output 0000H CP010 CR000 FFFFH As one shot pulse output Setting the same value to CR000 and CP010 is prohibited As pulse width measurement Using timer output TO00 is prohibited TOC00 00H 2 Timer start errors An error of up to one clock may occur in the time required for a match signal to be generated after timer start This is because counting TM00 is started as...

Page 239: ...TI010 pin was detected read the value of CR000 CR010 after INTTM000 INTTM010 is generated Figure 6 57 Timing of Holding Data by Capture Register N N 1 N 2 X N 1 M M 1 M 2 Count pulse TM00 count value Edge input INTTM010 Value captured to CR010 Capture read signal Capture operation is performed but read value is not guaranteed Capture operation b The values of CR000 and CR010 are not guaranteed aft...

Page 240: ... Operation Timing of OVF00 Flag FFFEH FFFFH FFFFH 0000H 0001H Count pulse TM00 INTTM000 OVF00 CR000 b Clearing OVF00 flag Even if the OVF00 flag is cleared to 0 after TM00 overflows and before the next count clock is counted before the value of TM00 becomes 0001H it is set to 1 again and clearing is invalid 8 One shot pulse output One shot pulse output operates correctly in the free running timer ...

Page 241: ...on is not performed but the INTTM000 signal is generated as an external interrupt signal Mask the INTTM000 signal when the external interrupt is not used 10 Edge detection a Specifying valid edge after reset If the operation of the 16 bit timer event counter 00 is enabled after reset and while the TI000 or TI010 pin is at high level and when the rising edge or both the edges are specified as the v...

Page 242: ... captured to the buffer are fixed when it is read The buffer however may not be updated when it is read immediately before the counter counts up because the buffer is updated at the timing the counter counts up Figure 6 59 16 bit Timer Counter 00 TM00 Read Timing Count clock TM00 count value 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 0034H 0035H 0037H 0038H 003BH Read buffer Read signal ...

Page 243: ...Configuration of 8 Bit Timer Event Counters 50 and 51 Item Configuration Timer register 8 bit timer counter 5n TM5n Register 8 bit timer compare register 5n CR5n Timer input TI5n Note Timer output TO5n Note Control registers Timer clock selection register 5n TCL5n 8 bit timer mode control register 5n TMC5n Port mode register 1 3 PM1 PM3 Note Port register 1 3 P1 P3 Note Note The port pins with whi...

Page 244: ...e 1 Note 2 Note 3 Note 3 Figure 7 2 Block Diagram of 8 Bit Timer Event Counter 51 Internal bus 8 bit timer compare register 51 CR51 TI51 TO51 P33 INTP3Note 3 Match Mask circuit OVF 3 Clear TCL512 TCL511 TCL510 Timer clock selection register 51 TCL51 Internal bus TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 Invert level 8 bit timer mode control register 51 TMC51 S R S Q R INV Selector INTTM51 To A D conve...

Page 245: ...CR5n can be read and written by an 8 bit memory manipulation instruction Except in PWM mode the value set in CR5n is constantly compared with the 8 bit timer counter 5n TM5n count value and an interrupt request INTTM5n is generated if they match In the PWM mode TO5n output becomes inactive when the values of TM5n and CR5n match but no interrupt is generated The value of CR5n can be set within 00H ...

Page 246: ...er 3 PM3 Note Port register 1 P1 or port register 3 P3 Note Note The port pins with which the I O pins for 8 bit timer event counters 50 and 51 are shared differ depending on the product as follows 78K0 KB2 A Shared with the pins of port 1 78K0 KC2 A Shared with the pins of port 3 1 Timer clock selection register 5n TCL5n This register sets the count clock of 8 bit timer event counter 5n and the v...

Page 247: ...an be used for the peripheral hardware clock fPRS differs depending on the power supply voltage Supply Voltage Use frequency range of peripheral hardware clock fPRS 2 7 V VDD 5 5 V fPRS 20 MHz 1 8 V VDD 2 7 V fPRS 5 MHz The values shown in the table above are those when fPRS fXH XSEL 1 2 Do not start timer operation with the external clock from the TI50 pin when the internal high speed oscillation...

Page 248: ... can be used for the peripheral hardware clock fPRS differs depending on the power supply voltage Supply Voltage Use frequency range of peripheral hardware clock fPRS 2 7 V VDD 5 5 V fPRS 20 MHz 1 8 V VDD 2 7 V fPRS 5 MHz The values shown in the table above are those when fPRS fXH XSEL 1 2 Do not start timer operation with the external clock from the TI51 pin when the internal high speed oscillati...

Page 249: ...ymbol 7 6 5 4 3 2 1 0 TMC50 TCE50 TMC506 0 0 LVS50 LVR50 TMC501 TOE50 TCE50 TM50 count operation control 0 After clearing to 0 count operation disabled counter stopped 1 Count operation start TMC506 TM50 operating mode selection 0 Mode in which clear start occurs on a match between TM50 and CR50 1 PWM free running mode LVS50 LVR50 Timer output F F status setting 0 0 No change 0 1 Timer output F F ...

Page 250: ...tive level selection 0 Inversion operation disabled Active high 1 Inversion operation enabled Active low TOE51 Timer output control 0 Output disabled TO51 output is low level 1 Output enabled Note Bits 2 and 3 are write only Cautions 1 The settings of LVS5n and LVR5n are valid in other than PWM mode 2 Perform 1 to 4 below in the following order not at the same time 1 Set TMC5n1 TMC5n6 Operation mo...

Page 251: ...be 0 or 1 Figure 7 9 Format of Port Mode Register 1 PM1 Address FF21H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM1 1 1 1 1 PM13 PM12 PM11 PM10 PM1n P1n pin I O mode selection n 0 to 3 0 Output mode output buffer on 1 Input mode output buffer off 78K0 KC2 A When using the P34 TO50 TI50 INTP2 and P33 TO51 TI51 INTP3 pins for timer output set PM34 PM33 and the output latches of P34 P33 to 0 When us...

Page 252: ... registers TCL5n Select the count clock CR5n Compare value TMC5n Stop the count operation select the mode in which clear start occurs on a match of TM5n and CR5n TMC5n 0000 0B Don t care 2 After TCE5n 1 is set the count operation starts 3 If the values of TM5n and CR5n match INTTM5n is generated TM5n is cleared to 00H 4 INTTM5n is generated repeatedly at the same interval Set TCE5n to 0 to stop th...

Page 253: ... Interval Timer Operation Timing 2 2 b When CR5n 00H t Interval time Count clock TM5n CR5n TCE5n INTTM5n 00H 00H 00H 00H 00H c When CR5n FFH t Count clock TM5n CR5n TCE5n INTTM5n 01H FEH FFH 00H FEH FFH 00H FFH FFH FFH Interval time Interrupt acknowledged Interrupt acknowledged Remark n 0 1 ...

Page 254: ... falling edge TCL5n 00H TI5n pin rising edge TCL5n 01H CR5n Compare value TMC5n Stop the count operation select the mode in which clear start occurs on match of TM5n and CR5n disable the timer F F inversion operation disable timer output TMC5n 00000000B 2 When TCE5n 1 is set the number of pulses input from the TI5n pin is counted 3 When the values of TM5n and CR5n match INTTM5n is generated TM5n i...

Page 255: ...ccurs on a match of TM5n and CR5n LVS5n LVR5n Timer Output F F Status Setting 0 1 Timer output F F clear 0 default value of TO5n output low level 1 0 Timer output F F set 1 default value of TO5n output high level Timer output enabled TMC5n 00001011B or 00000111B 2 After TCE5n 1 is set the count operation starts 3 The timer output F F is inverted by a match of TM5n and CR5n After INTTM5n is generat...

Page 256: ...rates as a PWM output when bit 6 TMC5n6 of 8 bit timer mode control register 5n TMC5n is set to 1 The duty pulse determined by the value set to 8 bit timer compare register 5n CR5n is output from TO5n Set the active level width of the PWM pulse to CR5n the active level can be selected with bit 1 TMC5n1 of TMC5n The count clock can be selected with bits 0 to 2 TCL5n0 to TCL5n2 of timer clock select...

Page 257: ...11 In case of 78K0 KB2 A P34 PM34 In case of 78K0 KC2 A 8 bit timer event counter 51 P10 PM10 In case of 78K0 KB2 A P33 PM33 In case of 78K0 KC2 A PWM output operation 1 PWM output TO5n output outputs an inactive level until an overflow occurs 2 When an overflow occurs the active level is output The active level is output until CR5n matches the count value of 8 bit timer counter 5n TM5n 3 After th...

Page 258: ...nactive level 5 Inactive level t 2 Active level b CR5n 00H Count clock TM5n CR5n TCE5n INTTM5n 01H 00H FFH 00H 01H 02H 00H FFH 00H 01H 02H M 00H TO5n L Inactive level t c CR5n FFH TM5n CR5n TCE5n INTTM5n TO5n 01H 00H FFH 00H 01H 02H FFH 1 Inactive level 2 Active level FFH 00H 01H 02H M 00H 3 Inactive level 2 Active level 5 Inactive level t Remarks 1 1 to 3 and 5 in Figure 7 14 a and c correspond t...

Page 259: ...M5n CR5n TCE5n INTTM5n TO5n 1 CR5n change N M N N 1 N 2 FFH 00H 01H M M 1 M 2 FFH 00H 01H 02H M M 1 M 2 N 02H M H 2 t b CR5n value is changed from N to M after clock rising edge of FFH Value is transferred to CR5n at second overflow Count clock TM5n CR5n TCE5n INTTM5n TO5n N N 1 N 2 FFH 00H 01H N N 1 N 2 FFH 00H 01H 02H N 02H N H M M M 1 M 2 1 CR5n change N M 2 t Caution When reading from CR5n bet...

Page 260: ...er Counter 5n TM5n Start Timing Count clock TM5n count value 00H 01H 02H 03H 04H Timer start 2 Reading of 8 bit timer counter 5n TM5n TM5n can be read without stopping the actual counter because the count values captured to the buffer are fixed when it is read The buffer however may not be updated when it is read immediately before the counter counts up because the buffer is updated at the timing ...

Page 261: ...t Timers H0 and H1 8 bit timers H0 and H1 include the following hardware Table 8 1 Configuration of 8 Bit Timers H0 and H1 Item Configuration Timer register 8 bit timer counter Hn Registers 8 bit timer H compare register 0n CMP0n 8 bit timer H compare register 1n CMP1n Timer output TOHn output controller Control registers 8 bit timer H mode register n TMHMDn 8 bit timer H carrier control register ...

Page 262: ...imer H mode register 0 TMHMD0 8 bit timer H compare register 10 CMP10 Decoder Selector Interrupt generator Output controller Level inversion PWM mode signal Timer H enable signal Clear 8 bit timer H compare register 00 CMP00 8 bit timer event counter 50 output Selector 8 bit timer counter H0 TOH0 P12 INT7 TI000 TOH0 output PM12 Output latch P12 fPRS fPRS 2 fPRS 22 fPRS 26 fPRS 210 Note Note 78K0 K...

Page 263: ...imer H carrier control register 1 TMCYC1 INTTMH1 INTTM51 Selector Interrupt generator Output controller Level inversion PM13 Output latch P13 1 0 F F R PWM mode signal Carrier generator mode signal Timer H enable signal 3 2 8 bit timer H compare register 01 CMP01 8 bit timer counter H1 Clear RMC1 NRZB1 NRZ1 Reload interrupt control 8 bit timer H mode register 1 TMHMD1 Selector TOH1 output fPRS fPR...

Page 264: ...e set to CMP1n with the count value of the 8 bit timer counter Hn and when the two values match inverts the output level of TOHn No interrupt request signal is generated In the carrier generator mode the CMP1n register always compares the value set to CMP1n with the count value of the 8 bit timer counter Hn and when the two values match generates an interrupt request signal INTTMHn At the same tim...

Page 265: ...H1 8 bit timer H mode register n TMHMDn 8 bit timer H carrier control register 1 TMCYC1 Note Port mode register 1 PM1 Port register 1 P1 Note 8 bit timer H1 only 1 8 bit timer H mode register n TMHMDn This register controls the mode of timer H This register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to 00H Remark n 0 1 ...

Page 266: ... level High level TOLEV0 0 1 Timer output level control in default mode Disables output Enables output TOEN0 0 1 Timer output control Other than above 7 6 5 4 3 2 1 0 fPRS Note 2 fPRS 2 fPRS 22 fPRS 26 fPRS 210 TM50 outputNote 4 Setting prohibited fPRS 2 MHz 2 MHz 1 MHz 500 kHz 31 25 kHz 1 95 kHz fPRS 5 MHz 5 MHz 2 5 MHz 1 25 MHz 78 13 kHz 4 88 kHz fPRS 10 MHz 10 MHz 5 MHz 2 5 MHz 156 25 kHz 9 77 ...

Page 267: ... 1 Start the operation of 8 bit timer event counter 50 first and then set the count clock to make the duty 50 It is not necessary to enable TOE50 1 TO50 output in any mode Cautions 1 When TMHE0 1 setting the other bits of TMHMD0 is prohibited However TMHMD0 can be refreshed the same value is written 2 In the PWM output mode be sure to set the 8 bit timer H compare register 10 CMP10 when starting t...

Page 268: ...t Enables output TOEN1 0 1 Timer output control 7 6 5 4 3 2 1 0 CKS12 0 0 0 0 1 1 1 1 CKS11 0 0 1 1 0 0 1 1 CKS10 0 1 0 1 0 1 0 1 Count clock selectionNote 1 fPRS Note 2 fPRS 22 fPRS 24 fPRS 26 fPRS 212 fRL 27 fRL 29 fRL fPRS 2 MHz 2 MHz 500 kHz 125 kHz 31 25 kHz 0 49 kHz 1 88 kHz TYP 0 47 kHz TYP 240 kHz TYP fPRS 5 MHz 5 MHz 1 25 MHz 312 5 kHz 78 13 kHz 1 22 kHz fPRS 10 MHz 10 MHz 2 5 MHz 625 kHz...

Page 269: ... output is determined depending on PM13 and P13 besides TOH1 output Note 78K0 KB2 A only Remarks 1 fPRS Peripheral hardware clock frequency 2 fRL Internal low speed oscillation clock frequency 2 8 bit timer H carrier control register 1 TMCYC1 This register controls the remote control output and carrier pulse output status of 8 bit timer H1 This register can be set by a 1 bit or 8 bit memory manipu...

Page 270: ...utput clear PM12 and PM13 and the output latches of P12 and P13 to 0 PM1 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets this register to FFH Note 78K0 KB2 A only Figure 8 8 Format of Port Mode Register 1 PM1 Address FF21H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM1 1 1 1 1 PM13 PM12 PM11 PM10 PM1n P1n pin I O mode selection n 0 to 3 0 Output mode out...

Page 271: ... During Interval Timer Square Wave Output Operation i Setting timer H mode register n TMHMDn 0 0 1 0 1 0 1 0 0 0 1 0 1 TMMDn0 TOLEVn TOENn CKSn1 CKSn2 TMHEn TMHMDn CKSn0 TMMDn1 Timer output setting Default setting of timer output level Interval timer mode setting Count clock fCNT selection Count operation stopped ii CMP0n register setting The interval time is as follows if N is set as a comparison...

Page 272: ...r 3 1 1 The count operation is enabled by setting the TMHEn bit to 1 The count clock starts counting no more than 1 clock after the operation is enabled 2 When the value of the 8 bit timer counter Hn matches the value of the CMP0n register the value of the timer counter is cleared and the level of the TOHn output is inverted In addition the INTTMHn signal is output at the rising edge of the count ...

Page 273: ...Output Operation 2 2 b Operation when CMP0n FFH 00H Count clock Count start 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn 01H FEH Clear Clear FFH 00H FEH FFH 00H FFH Interval time c Operation when CMP0n 00H 00H 00H Count clock Count start 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn Interval time Remark n 0 1 ...

Page 274: ...TMMDn0 TOLEVn TOENn CKSn1 CKSn2 TMHEn TMHMDn CKSn0 TMMDn1 Timer output enabled Default setting of timer output level PWM output mode selection Count clock fCNT selection Count operation stopped ii Setting CMP0n register Compare value N Cycle setting iii Setting CMP1n register Compare value M Duty setting Remarks 1 n 0 1 2 00H CMP1n M CMP0n N FFH 2 The count operation starts when TMHEn 1 3 The CMP0...

Page 275: ...akes a duration of three operating clocks signal selected by the CKSn2 to CKSn0 bits of the TMHMDn register from when the value of the CMP1n register is changed until the value is transferred to the register 2 Be sure to set the CMP1n register when starting the timer count operation TMHEn 1 after the timer count operation was stopped TMHEn 0 be sure to set again even if setting the same value to t...

Page 276: ...ock to count up At this time PWM output outputs an inactive level 2 When the values of the 8 bit timer counter Hn and the CMP0n register match an active level is output At this time the value of the 8 bit timer counter Hn is cleared and the INTTMHn signal is output 3 When the values of the 8 bit timer counter Hn and the CMP1n register match an inactive level is output At this time the 8 bit timer ...

Page 277: ...CMP0n FFH CMP1n 00H Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 00H 01H FFH 00H 01H 02H FFH 00H FFH 00H 01H 02H CMP1n FFH 00H c Operation when CMP0n FFH CMP1n FEH Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H CMP1n FFH FEH Remark n 0 1 ...

Page 278: ...nual U19780EJ2V0UD 276 Figure 8 12 Operation Timing in PWM Output Mode 3 4 d Operation when CMP0n 01H CMP1n 00H Count clock 8 bit timer counter Hn CMP0n TMHEn INTTMHn TOHn TOLEVn 0 01H 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP1n 00H Remark n 0 1 ...

Page 279: ...Hn is cleared an active level is output and the INTTMHn signal is output 4 If the CMP1n register value is changed the value is latched and not transferred to the register When the values of the 8 bit timer counter Hn and the CMP1n register before the change match the value is transferred to the CMP1n register and the CMP1n register value is changed 2 However three count clocks or more are required...

Page 280: ...utput 1 Carrier generation In carrier generator mode the 8 bit timer H compare register 01 CMP01 generates a low level width carrier pulse waveform and the 8 bit timer H compare register 11 CMP11 generates a high level width carrier pulse waveform Rewriting the CMP11 register during the 8 bit timer H1 operation is possible but rewriting the CMP01 register is prohibited 2 Carrier output control Car...

Page 281: ...ount clock of the 8 bit timer H1 and is output as the INTTM5H1 signal 2 The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the INTTM5H1 signal 3 Write the next value to the NRZB1 bit in the interrupt servicing program that has been started by the INTTM5H1 interrupt or after timing has been checked by polling the interrupt request flag Write data t...

Page 282: ...he 8 bit timer counter H1 and the CMP01 register value match the INTTMH1 signal is generated the 8 bit timer counter H1 is cleared At the same time the compare register to be compared with the 8 bit timer counter H1 is switched from the CMP01 register to the CMP11 register 5 When the count value of the 8 bit timer counter H1 and the CMP11 register value match the INTTMH1 signal is generated the 8 ...

Page 283: ...TMHE1 0 be sure to set again even if setting the same value to the CMP11 register 2 Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock frequency of TM51 3 Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH 4 The set value of the CMP11 register can be changed while the timer counter is operating However it takes the duration of three operat...

Page 284: ... carrier clock signal is inverted and the compare register to be compared with the 8 bit timer counter H1 is switched from the CMP01 register to the CMP11 register The 8 bit timer counter H1 is cleared to 00H 4 When the count value of the 8 bit timer counter H1 matches the CMP11 register value the INTTMH1 signal is generated the carrier clock signal is inverted and the compare register to be compa...

Page 285: ... be compared with the 8 bit timer counter H1 is switched from the CMP01 register to the CMP11 register The 8 bit timer counter H1 is cleared to 00H 4 When the count value of the 8 bit timer counter H1 matches the CMP11 register value the INTTMH1 signal is generated the carrier clock signal is inverted and the compare register to be compared with the 8 bit timer counter H1 is switched from the CMP1...

Page 286: ...nged while the 8 bit timer H1 is operating The new value L to which the value of the register is to be changed is latched When the count value of the 8 bit timer counter H1 matches the value M of the CMP11 register before the change the CMP11 register is changed 3 However it takes three count clocks or more since the value of the CMP11 register has been changed until the value is transferred to th...

Page 287: ...al Time Counter The real time counter has the following features Having counters of year month week day hour minute and second and can count up to 99 years Constant period interrupt function period 1 month to 0 5 seconds Alarm interrupt function alarm week hour minute Interval interrupt function Pin output function of 1 Hz Pin output function of 512 Hz or 16 384 kHz or 32 768 kHz ...

Page 288: ...egister 0 RTCC0 Real time counter control register 1 RTCC1 Real time counter control register 2 RTCC2 Sub count register RSUBC Second count register SEC Minute count register MIN Hour count register HOUR Day count register DAY Week count register WEEK Month count register MONTH Year count register YEAR Watch error correction register SUBCUD Alarm minute register ALARMWM Alarm hour register ALARMWH...

Page 289: ...register ALARMWH 6 bit Alarm minute register ALARMWM 7 bit Year count register YEAR 8 bit Month count register MONTH 5 bit Week count register WEEK 3 bit Day count register DAY 6 bit Hour count register HOUR 6 bit Minute count register MIN 7 bit Second count register SEC 7 bit Wait control Output latch P41 0 5 seconds Sub count register RSUBC 16 bit Count clock 32 768 kHz Selector Buffer Buffer Bu...

Page 290: ...Real time counter control register 0 RTCC0 The RTCC0 register is an 8 bit register that is used to start or stop the real time counter operation control the RTCCL and RTC1HZ pins and set a 12 or 24 hour system and the constant period interrupt function RTCC0 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to 00H ...

Page 291: ...e displayed time digits that are displayed CT2 CT1 CT0 Constant period interrupt INTRTC selection 0 0 0 Does not use constant period interrupt function 0 0 1 Once per 0 5 s synchronized with second count up 0 1 0 Once per 1 s same time as second count up 0 1 1 Once per 1 m second 00 of every minute 1 0 0 Once per 1 hour minute 00 and second 00 of every hour 1 0 1 Once per 1 day hour 00 minute 00 a...

Page 292: ... each alarm register WALIE flag of RTCC1 the ALARMWM register the ALARMWH register and the ALARMWW register set match operation to be disable 0 for the WALE bit WALIE Control of alarm interrupt INTRTC function operation 0 Does not generate interrupt on matching of alarm 1 Generates interrupt on matching of alarm WAFG Alarm detection status flag 0 Alarm mismatch 1 Detection of matching of alarm Thi...

Page 293: ...lue Because RSUBC continues operation complete reading or writing of it in 1 second and clear this bit back to 0 When RWAIT 1 it takes up to 1 clock 32 768 kHz until the counter value can be read or written If RSUBC overflows when RWAIT 1 it counts up after RWAIT 0 If the second count register is written however it does not count up because RSUBC is cleared Caution The RIFG and WAFG flags may be c...

Page 294: ...5 ms 1 0 0 1 2 7 fSUB 3 90625 ms 1 0 1 0 2 8 fSUB 7 8125 ms 1 0 1 1 2 9 fSUB 15 625 ms 1 1 0 0 2 10 fSUB 31 25 ms 1 1 0 1 2 11 fSUB 62 5 ms 1 1 1 2 12 fSUB 125 ms RCLOE2 Note RTCDIV pin output control 0 Output of RTCDIV pin is disabled 1 Output of RTCDIV pin is enabled RCKDIV Selection of RTCDIV pin output frequency 0 RTCDIV pin outputs 512 Hz 1 95 ms 1 RTCDIV pin outputs 16 384 kHz 0 061 ms Note ...

Page 295: ...is changing is read Figure 9 5 Format of Sub Count Register RSUBC RSUBC FFB1H FFB0H Address FF70H FF71H After reset 0000H R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 Second count register SEC The SEC register is an 8 bit register that takes a value of 0 to 59 decimal and indicates the count value of seconds It counts up when the sub counter overflows When data is written to this register it is writt...

Page 296: ... MIN10 MIN8 MIN4 MIN2 MIN1 7 Hour count register HOUR The HOUR register is an 8 bit register that takes a value of 00 to 23 or 01 to 12 21 to 32 decimal and indicates the count value of hours It counts up when the minute counter overflows When data is written to this register it is written to a buffer and then to the counter up to 2 clocks 32 768 kHz later Set a decimal value of 00 to 23 01 to 12 ...

Page 297: ...25H 18 18H 6 p m 26H 19 19H 7 p m 27H 20 20H 8 p m 28H 21 21H 9 p m 29H 22 22H 10 p m 30H 23 23H 11 p m 31H The HOUR register value is set to 12 hour display when the AMPM bit is 0 and to 24 hour display when the AMPM bit is 1 In 12 hour display the fifth bit of the HOUR register displays 0 for AM and 1 for PM 8 Day count register DAY The DAY register is an 8 bit register that takes a value of 1 t...

Page 298: ...tes the count value of weekdays It counts up in synchronization with the day counter When data is written to this register it is written to a buffer and then to the counter up to 2 clocks 32 768 kHz later Set a decimal value of 00 to 06 to this register in BCD code If a value outside the range is set the register value returns to the normal value after 1 period WEEK can be set by an 8 bit memory m...

Page 299: ... Address FF77H After reset 01H R W Symbol 7 6 5 4 3 2 1 0 MONTH 0 0 0 MONTH10 MONTH8 MONTH4 MONTH2 MONTH1 11 Year count register YEAR The YEAR register is an 8 bit register that takes a value of 0 to 99 decimal and indicates the count value of years It counts up when the month counter overflows Values 00 04 08 92 and 96 indicate a leap year When data is written to this register it is written to a ...

Page 300: ...onds F6 Setting of watch error correction value 0 Increases by F5 F4 F3 F2 F1 F0 1 2 1 Decreases by F5 F4 F3 F2 F1 F0 1 2 When F6 F5 F4 F3 F2 F1 F0 0 0 0 0 0 the watch error is not corrected is 0 or 1 F5 to F0 are the inverted values of the corresponding bits 000011 when 111100 Range of correction value when F6 0 2 4 6 8 120 122 124 when F6 1 2 4 6 8 120 122 124 The range of value that can be corr...

Page 301: ...ruction Reset signal generation clears this register to 12H However the value of this register is 00H if the AMPM bit is set to 1 after reset Caution Set a decimal value of 00 to 23 01 to 12 or 21 to 32 to this register in BCD code If a value outside the range is set the alarm is not detected Figure 9 15 Format of Alarm Hour Register ALARMWH Address FF7BH After reset 12H R W Symbol 7 6 5 4 3 2 1 0...

Page 302: ... 30 p m 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 Monday Wednesday Friday 11 59 p m 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 16 Port mode register 4 PM4 This register sets port 4 input output in 1 bit units When using the P40 RTCDIV RTCCL pin for clock output real time counter and P41 RTC1HZ pins for clock output of real time counter correction clear PM40 and PM41 and the output latches of P40 and P41 to 0 PM4 is set by...

Page 303: ...CT2 to CT0 Selects 12 24 hour system and interrupt INTRTC Sets second count register Sets minute count register No Yes Setting HOUR Sets hour count register Setting WEEK Sets week count register Setting DAY Sets day count register Setting MONTH Sets month count register Setting YEAR Sets year count register Clearing IF flags of interrupt Clears interrupt request flags RTCIF RTCIIF Clearing MK flag...

Page 304: ...ing HOUR Reads hour count register Reading WEEK Reads week count register Reading DAY Reads day count register Reading MONTH Reads month count register Reading YEAR Reads year count register RWAIT 0 RWST 0 Note No Yes Sets counter operation Checks wait status of counter End Note Be sure to confirm that RWST 0 before setting STOP mode Caution Complete the series of operations of setting RWAIT to 1 ...

Page 305: ...Checks wait status of counter End Writes second count register Writes minute count register Writes hour count register Writes week count register Writes day count register Writes month count register Writes year count register Note Be sure to confirm that RWST 0 before setting STOP mode Caution Complete the series of operations of setting RWAIT to 1 to clearing RWAIT to 0 within 1 second Remark SE...

Page 306: ...ALARMWH Sets alarm hour register Setting ALARMWW Sets alarm week register WALE 1 Match operation of alarm is valid WAFG 1 No Yes Constant period interrupt servicing Match detection of alarm No Remarks 1 ALARMWM ALARMWH and ALARMWW may be written in any sequence 2 Fixed cycle interrupts and alarm match interrupts use the same interrupt source INTRTC When using these two types of interrupts at the s...

Page 307: ...st Figure 9 23 32 768 kHz Output Setting Procedure RTCE 0 RTCE 1 Start Stops counter operation RCLOE0 1 Enables output of RTCCL pin 32 768 kHz Starts counter operation 32 768 kHz output start from RTCCL pin 9 4 6 512 Hz 16 384 kHz output of real time counter Set outputs of 512 Hz and 16 768 kHz after setting 0 to RTCE first Figure 9 24 512 Hz 16 384 kHz output Setting Procedure RTCE 0 RTCE 1 Start...

Page 308: ...s in 1 minute Oscillation frequency Target frequency 1 32768 60 Note The correction value is the watch error correction value calculated by using bits 6 to 0 of the watch error correction register SUBCUD When F6 0 Correction value F5 F4 F3 F2 F1 F0 1 2 When F6 1 Correction value F5 F4 F3 F2 F1 F0 1 2 When F6 F5 F4 F3 F2 F1 F0 is 0 0 0 0 0 watch error correction is not performed is 0 or 1 F5 to F0 ...

Page 309: ...Hz If the target frequency is assumed to be 32768 Hz 32772 3 Hz 131 2 ppm the correction range for 131 2 ppm is 63 1 ppm or less so assume DEV to be 0 The expression for calculating the correction value when DEV is 0 is applied Correction value Number of correction counts in 1 minute 3 Oscillation frequency Target frequency 1 32768 60 3 32772 3 32768 1 32768 60 3 86 Calculating the values to be se...

Page 310: ... F6 F5 F4 F3 F2 F1 F0 0 0 1 0 1 1 0 0 RSUBC count value SEC 00 01 8055H 0000H 0001H 7FFFH 0000H 8054H 40 8055H 0000H 8054H 8055H 0000H 8054H 19 0000H 0001H 7FFFH 20 39 0000H 0001H 7FFFH 0000H 0001H 7FFFH 59 00 8055H 0000H 8054H 7FFFH 56H 86 7FFFH 56H 86 7FFFH 56H 86 7FFFH 56H 86 Count start ...

Page 311: ...Oscillation frequency 32768 0 9999817 32767 4 Hz Assume the target frequency to be 32768 Hz 32767 4 Hz 18 3 ppm and DEV to be 1 The expression for calculating the correction value when DEV is 1 is applied Correction value Number of correction counts in 1 minute Oscillation frequency Target frequency 1 32768 60 32767 4 32768 1 32768 60 36 Calculating the values to be set to F6 to F0 When the correc...

Page 312: ...tion when DEV F6 F5 F4 F3 F2 F1 F0 1 1 1 0 1 1 1 0 RSUBC count value SEC 00 01 7FDBH 0000H 0001H 7FFFH 0000H 7FDAH 40 19 0000H 0001H 7FFFH 0000H 0001H 7FFFH 20 39 0000H 0001H 7FFFH 0000H 0001H 7FFFH 0000H 0001H 7FFFH 59 00 7FDBH 0000H 7FDAH 7FFFH 24H 36 7FFFH 24H 36 Count start ...

Page 313: ...anipulation instruction is executed on the watchdog timer enable register WDTE If data other than ACH is written to WDTE If data is written to WDTE during a window close period If the instruction is fetched from an area not set by the IMS register detection of an invalid check while the CPU hangs up If the CPU accesses an area that is not set by the IMS register excluding FB00H to FFCFH and FFE0H ...

Page 314: ...indow open period Bits 6 and 5 WINDOW1 WINDOW0 Controlling counter operation of watchdog timer Bit 4 WDTON Overflow time of watchdog timer Bits 3 to 1 WDCS2 to WDCS0 Remark For the option byte see CHAPTER 24 OPTION BYTE Figure 10 1 Block Diagram of Watchdog Timer fRL 2 Clock input controller Reset output controller Internal reset signal Internal bus Selector 17 bit counter 210 fRL to 217 fRL Watch...

Page 315: ...N setting value of the option byte 0080H To operate watchdog timer set WDTON to 1 WDTON Setting Value WDTE Reset Value 0 watchdog timer count operation disabled 1AH 1 watchdog timer count operation enabled 9AH Cautions 1 If a value other than ACH is written to WDTE an internal reset signal is generated If the source clock to the watchdog timer is stopped however an internal reset signal is generat...

Page 316: ...tchdog timer is cleared and starts counting again 4 After that write WDTE the second time or later after a reset release during the window open period If WDTE is written during a window close period an internal reset signal is generated 5 If the overflow time expires without ACH written to WDTE an internal reset signal is generated A internal reset signal is generated in the following cases If a 1...

Page 317: ...edge time is delayed Set the overflow time and window size taking this delay into consideration 10 4 2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by using bits 3 to 1 WDCS2 to WDCS0 of the option byte 0080H If an overflow occurs an internal reset signal is generated The present count is cleared and the watchdog timer starts counting again by writing ACH to ...

Page 318: ...nternal reset signal is generated if ACH is written to WDTE Caution The first writing to WDTE after a reset release clears the watchdog timer if it is made before the overflow time regardless of the timing of the writing and the watchdog timer starts counting again The window open period to be set is as follows Table 10 4 Setting Window Open Period of Watchdog Timer WINDOW1 WINDOW0 Window Open Per...

Page 319: ... 100 Window close time 0 to 7 11 ms 0 to 4 74 ms 0 to 2 37 ms None Window open time 7 11 to 7 76 ms 4 74 to 7 76 ms 2 37 to 7 76 ms 0 to 7 76 ms When window open period is 25 Overflow time 211 fRL MAX 2 11 264 kHz MAX 7 76 ms Window close time 0 to 211 fRL MIN 1 0 25 0 to 2 11 216 kHz MIN 0 75 0 to 7 11 ms Window open time 211 fRL MIN 1 0 25 to 2 11 fRL MAX 2 11 216 kHz MIN 0 75 to 2 11 264 kHz MA...

Page 320: ... during remote controlled transmission and clock output for supply to peripheral ICs The clock selected with the clock output selection register CKS is output Figure 11 1 shows the block diagram of clock output controller Figure 11 1 Block Diagram of Clock Output Controller CLOE 8 PCL P42 SSI10 INTP9 Clock controller Prescaler Internal bus CCS3 Clock output select register CKS CCS2 CCS1 CCS0 Outpu...

Page 321: ...ction register CKS Port mode register 4 PM4 Port register 4 P4 11 3 Registers Controlling Clock Output Controller The following two registers are used to control the clock output controller Clock output selection register CKS Port mode register 4 PM4 1 Clock output selection register CKS This register sets output enable disable for clock output PCL and sets the output clock CKS is set by a 1 bit o...

Page 322: ...12 5 kHz 625 kHz 0 1 1 0 fPRS 2 6 156 25 kHz 312 5 kHz 0 1 1 1 fPRS 2 7 78 125 kHz 156 25 kHz 1 0 0 0 fSUB 32 768 kHz Other than above Setting prohibited Notes 1 The frequency that can be used for the peripheral hardware clock fPRS differs depending on the power supply voltage Supply Voltage Use frequency range of peripheral hardware clock fPRS 2 7 V VDD 5 5 V fPRS 20 MHz 1 8 V VDD 2 7 V fPRS 5 MH...

Page 323: ...n 1 Input mode output buffer off 11 4 Operations of Clock Output Controller 11 4 1 Operation as clock output The clock pulse is output as the following procedure 1 Select the clock pulse output frequency with bits 0 to 3 CCS0 to CCS3 of the clock output selection register CKS clock pulse output in disabled status 2 Set bit 4 CLOE of CKS to 1 to enable clock output Remark The clock output controlle...

Page 324: ...nd is configured to control a total of twelve channels of analog inputs including up to twelve channels of A D converter analog inputs ANI0 to ANI6 ANI8 to ANI11 ANI13 In products with operational amplifier ANI1 ANI4 and ANI9 functions alternately as operational amplifier 0 1 and 2 output AMP0OUT AMP1OUT AMP2OUT This enables using operational amplifier output as an analog input source The operatio...

Page 325: ...I15 AVREFM P27 AVSS ADCS bit ADREF bit ADREFM AVREFM ANI15 P27 AVDD ADREF VRGV AVREFP ADREFP Selector Selector Sample hold circuit A D Voltage comparator Successive approximation register SAR Controller Tap selector Series resistor string A D conversion result register ADCR Internal bus A D converter mode register 1 ADM1 Analog input channel specification register ADS A D converter mode register A...

Page 326: ... voltage to be compared with the sampled voltage value Figure 12 2 Circuit Configuration of Series Resistor String ADCS Series resistor string ADREFP P ch ADREFM Note In the case of 78K0 KB2 A the series resistor string is connected between AVREF and AVSS 4 Voltage comparator The voltage comparator compares the sampled voltage value and the output voltage of the series resistor string 5 Successive...

Page 327: ...his pin at the same potential as that of the VSS pin even when the A D converter is not used In the 48 pin versions of 78K0 KC3 A the ground potential AVSS can also be used as the negative reference voltage for the A D converter ADREFM Clear AVREF bit of ADVRC register to 0 when using AVSS as ADREFM 11 ADREFP pin Note 1 This pin is used to input the external reference voltage AVREFP The analog sig...

Page 328: ...ight registers A D converter mode register ADM A D converter mode register 1 ADM1 Analog conference voltage control register ADVRC 12 bit A D conversion result register ADCR 8 bit A D conversion result register ADCRH Analog input channel specification register ADS A D port configuration register ADPC Port mode registers 2 8 PM2 PM8 ...

Page 329: ...ltage comparator operation ADCE 0 1 Select operation mode of A D convert Continuously convert mode Single convert mode ADSCM 0 1 Notes 1 For details of FR2 to FR0 LV1 LV0 and A D conversion see Table 12 2 A D Conversion Time Selection 2 The operation of the A D voltage comparator is controlled by ADCS and ADCE and it takes 1 μs from operation start to operation stabilization Therefore when ADCS is...

Page 330: ... LV0 to values other than the identical data 2 When using the A D converter in normal mode 2 LV1 0 LV0 1 or low voltage mode LV1 1 LV0 0 enable A D conversion by setting ADCE to 1 after starting up the A D converter voltage booster by setting VRGV to 1 and waiting for the reference voltage stabilization time 10 μ s to elapse Note that it takes the A D voltage comparator 1 μs to stabilize after bei...

Page 331: ...U 8 MHz fCPU 10 MHz fCPU 20 MHz Conversion Clock fAD 0 0 0 240 fCPU 30 μs 24 μs 12 μs fCPU 12 0 0 1 160 fCPU 20 μs 16 μs 8 μs fCPU 8 0 1 0 120 fCPU 15 μs 12 μs 6 μs fCPU 6 0 1 1 100 fCPU 12 5 μs 10 μs 5 μs fCPU 5 1 0 0 80 fCPU 10 μs 8 μs fCPU 4 1 0 1 60 fCPU Setting prohibited 7 5 μs 6 μs fCPU 3 1 1 0 40 fCPU 40 μs 5 μs fCPU 2 1 1 1 0 1 20 fCPU 20 μs Setting prohibited Setting prohibited Setting p...

Page 332: ...mode 2 or low voltage mode be sure to enable the A D converter voltage booster by setting VRGV to 1 Caution The CPU clock fCPU is supplied to the A D converter s clock If fCPU is changed therefore the A D converter s conversion clock fAD is also changed When changing fCPU by changing the setting of the PCC register or the MCM register therefore be sure to stop the A D converter first by setting AD...

Page 333: ...ersion start trigger ADM1 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to 00H Figure 12 6 Format of A D Converter Mode Register 1 ADM1 Address FF3AH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADM1 ADTMD 0 0 0 0 0 0 ADTRS ADTMD A D trigger mode selection 0 Software trigger mode 1 Timer trigger mode hardware trigger mode ADTRS Timer trig...

Page 334: ...ence voltage for the A D converter selection 0 AVSS 1 AVREFM external conference voltage input VRGV Note 2 A D converter booster circuit operation control 0 Stop operation 1 Enables operation Notes 1 As the AVREFM is not mounted on 78K0 KB2 A Clear the ADREF to 0 2 When using the A D converter in normal mode 2 LV1 0 LV0 1 or low voltage mode LV1 1 LV0 0 enable A D conversion by setting ADCE to 1 a...

Page 335: ...rsion result following conversion completion before writing to ADM ADS and ADPC Using timing other than the above may cause an incorrect conversion result to be read 5 8 bit A D conversion result register ADCRH This register is an 8 bit register that stores the A D conversion result The higher 8 bits of 12 bit resolution are stored ADCRH can be read by an 8 bit memory manipulation instruction Rese...

Page 336: ...S3 ADS2 ADS1 ADS0 Analog input channel 0 0 0 0 ANI0 0 0 0 1 ANI1 0 0 1 0 ANI2 0 0 1 1 ANI3 0 1 0 0 ANI4 0 1 0 1 ANI5 0 1 1 0 ANI6 0 1 1 1 Setting prohibited 1 0 0 0 ANI8 1 0 0 1 ANI9 1 0 1 0 ANI10 1 0 1 1 ANI11 1 1 1 1 ANI15 Other than the above Setting prohibited Note In case of 78K0 KB2 A setting prohibited Cautions 1 Be sure to clear bits 4 to 7 to 0 2 Set a channel to be used for A D conversio...

Page 337: ...I10 AMP2 P82 ANI9 AMP2OUT P81 ANI8 AMP2 P80 ANI6 P26 ANI5 AMP1 P25 ANI4 AMP1OUT P24 ANI3 AMP1 P23 ANI2 AMP0 P22 ANI1 AMP0OUT P21 ANI0 AMP0 P20 0 0 0 0 0 A A A A A A A A A A A A 0 0 0 0 1 A A A A A A A A A A A D 0 0 0 1 0 A A A A A A A A A A D D 0 0 0 1 1 A A A A A A A A A D D D 0 0 1 0 0 A A A A A A A A D D D D 0 0 1 0 1 A A A A A A A D D D D D 0 0 1 1 0 A A A A A A D D D D D D 0 0 1 1 1 Setting p...

Page 338: ...analog input port not the pin level but 0 is always read Remark 78K0 KB2 A ANI0 to ANI5 ANI8 to ANI11 78K0 KC2 A ANI0 to ANI6 ANI8 to ANI11 ANI15 Figure 12 12 Format of Port Mode Registers 2 and 8 PM2 PM8 1 μ PD78F0590 78F0591 30 pin products Address FF22H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 PM25 PM24 PM23 PM22 PM21 PM20 Address FF28H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM8 1...

Page 339: ...elect ANI Operational amplifier input Analog input selection Output mode Setting prohibited Table 12 4 Setting Functions of ANI1 AMP0OUT P21 ANI4 AMP1OUT P24 ANI9 AMP2OUT P81 Pins ADPC Register PM2 PM8 Register OAENn bit ADS Register ANI1 AMP0OUT P21 ANI4 AMP1OUT P24 ANI9 AMP2OUT P81 Pins 0 Digital input Input mode 1 Setting prohibited 0 Digital output Digital I O selection Output mode 1 Setting p...

Page 340: ...election Output mode Setting prohibited Remark 78K0 KB2 A ANI11 P83 only 78K0 KC2 A ANI6 P26 ANI11 P83 Table 12 6 Setting Functions of ANI15 AVREFM P27 pin 78K0 KC2 A only ADPC Register PM2 Register ADREF bit ADS Register ANI15 AVREFM P27 pin 0 Digital input Input mode 1 Setting prohibited 0 Digital output Digital I O selection Output mode 1 Setting prohibited Selects ANI Analog input to be conver...

Page 341: ...put channel is sampled by the sample hold circuit 9 When sampling has been done for a certain time the sample hold circuit is placed in the hold state and the sampled voltage is held until the A D conversion operation has ended 10 Bit 11 of the successive approximation register SAR is set The series resistor string voltage tap is set to 1 2 AVREF by the tap selector 11 The voltage difference betwe...

Page 342: ...D conversion 3 When using the A D converter in normal mode 2 LV1 0 LV0 1 or low voltage mode LV1 1 LV0 0 enable A D conversion by setting ADCE to 1 after starting up the A D converter voltage booster by setting VRGV to 1 and waiting for the reference voltage stabilization time 10 μ s to elapse Note that it takes the A D voltage comparator 1 μs to stabilize after being enabled The validity of the d...

Page 343: ...entheses VAIN Analog input voltage AVREF Conference voltage of A D converter ADCR 12 bit A D conversion result register ADCR value Remark 78K0 KB2 A ANI0 to ANI5 ANI8 to ANI11 78K0 KC2 A ANI0 to ANI6 ANI8 to ANI11 ANI15 Figure 12 14 shows the relationship between the analog input voltage and the A D conversion result Figure 12 14 Relationship Between Analog Input Voltage and A D Conversion Result ...

Page 344: ... next A D conversion operation is immediately started 3 If 1 is written to ADCS during A D conversion the A D conversion operation under execution is stopped and restarted from the beginning At this time the conversion result immediately before is retained 4 If ADS is rewritten during A D conversion the A D conversion operation under execution is stopped and restarted from the beginning At this ti...

Page 345: ...ution is stopped and restarted from the beginning At this time the conversion result immediately before is retained 4 If ADS is rewritten during A D conversion the A D conversion operation under execution is stopped and restarted from the beginning At this time the conversion result immediately before is retained 5 If 0 is written to ADCS during A D conversion A D conversion is immediately stopped...

Page 346: ...A D conversion the A D conversion operation under execution is stopped and restarted from the beginning At this time the conversion result immediately before is retained 6 If 0 is written to ADCS during A D conversion A D conversion immediately stops and the A D converter waits for a timer trigger At this time the conversion result immediately before is retained 7 When 0 is written to ADTMD while ...

Page 347: ...he start of the next conversion 5 If a timer trigger signal is generated during A D conversion the A D conversion operation under execution is stopped and restarted from the beginning At this time the conversion result immediately before is retained 6 When 0 is written to ADTMD while A D conversion operation is stopped ADCS 0 the software trigger mode is set and A D conversion operation is not sta...

Page 348: ...A D conversion In timer trigger mode ADCS is automatically set to 1 and A D conversion starts when the timer trigger signal is generated 8 When one A D conversion has been completed an interrupt request signal INTAD is generated 9 Transfer the A D conversion data to the A D conversion result register ADCR ADCRH 10 In successive conversion mode The next A D conversion starts automatically In single...

Page 349: ... settings of the operational amplifier during A D conversion 6 When using the A D converter in normal mode 2 LV1 0 LV0 1 or low voltage mode LV1 1 LV0 0 enable A D conversion by setting ADCE to 1 after starting up the A D converter voltage booster by setting VRGV to 1 and waiting for the reference voltage stabilization time 10 μ s to elapse Note that it takes the A D voltage comparator 1 μs to sta...

Page 350: ...overall error in the characteristics table 3 Quantization error When analog values are converted to digital values a 1 2LSB error naturally occurs In an A D converter an analog input voltage in a range of 1 2LSB is converted to the same digital code so a quantization error cannot be avoided Note that the quantization error is not included in the overall error zero scale error full scale error inte...

Page 351: ... and the ideal value Figure 12 21 Zero Scale Error Figure 12 22 Full Scale Error 111 011 010 001 Zero scale error Ideal line 000 0 1 2 3 AVREF Digital output Lower 3 bits Analog input LSB 111 110 101 000 0 AVREF 3 Full scale error Ideal line Analog input LSB Digital output Lower 3 bits AVREF 2 AVREF 1 AVREF Figure 12 23 Integral Linearity Error Figure 12 24 Differential Linearity Error 0 AVREF Dig...

Page 352: ...affected 3 Conflicting operations 1 Conflict between A D conversion result register ADCR ADCRH write and ADCR or ADCRH read by instruction upon the end of conversion ADCR or ADCRH read has priority After the read operation the new conversion result is written to ADCR or ADCRH 2 Conflict between ADCR or ADCRH write and A D converter mode register ADM write analog input channel specification registe...

Page 353: ...he A D conversion may not be obtained due to coupling noise Make sure that a digital pulse is not input to or output from pins adjacent to the pin whose signal is being A D converted 3 If any of the pins of port 2 or 8 is being used as a digital output port during A D conversion the expected A D conversion value might not be able to be obtained due to coupling noise Make sure therefore that a digi...

Page 354: ...rite Caution is therefore required since at this time when ADIF is read immediately after the ADS rewrite ADIF is set despite the fact A D conversion for the post change analog input has not ended When A D conversion is stopped and then resumed clear ADIF before the A D conversion operation is resumed Figure 12 26 Timing of A D Conversion End Interrupt Request Generation ADS rewrite start of ANIn ...

Page 355: ...ompletion before writing to ADM1 ADS and ADPC Using a timing other than the above may cause an incorrect conversion result to be read 11 Internal equivalent circuit The equivalent circuit of the analog input block is shown below Figure 12 27 Internal Equivalent Circuit of ANIn Pin ANIn C1 C2 R1 Table 12 7 Resistance and Capacitance Values of Equivalent Circuit Reference Values AVDD R1 C1 C2 2 3 V ...

Page 356: ...lified voltage can be used as an analog input of the A D converter because the AMPnOUT pin is alternatively used with analog input pin of the A D converter Remark n 0 2 13 2 Configuration of Operational Amplifier The operational amplifier consists of the following hardware Table 13 1 Configuration of Operational Amplifier Item Configuration Operational amplifier input AMPn pin AMPn pin Operational...

Page 357: ... amplifier voltage controller AMP0 ANI2 P22 OAEN0 bit AMP0 ANI0 P20 AMP0OUT ANI1 P21 AMP0 _ Operational amplifier 0 To A D converter Internal bus OAIM0 OAEN2 OAEN1 OAEN0 OAIM1 AMP1 ANI5 P25 OAEN1 bit AMP1 ANI3 P23 AMP1OUT ANI4 P24 AMP1 _ Operational amplifier 1 To A D converter AMP2 ANI10 P82 AMP2 ANI8 P80 AMP2OUT ANI9 P81 AMP2 _ Operational amplifier 2 To A D converter ...

Page 358: ...IM0 Operational amplifier operation mope 0 0 Mode 2 Slew rate 0 4 V μs TYP 0 1 Mode 3 Slew rate 1 4 V μs TYP 1 0 Setting prohibited 1 1 Mode 1 Slew rate 0 2 V μs TYP OAEN2 Operational amplifier 2 operation control 0 Stops operational amplifier 2 operation 1 Enables operational amplifier 2 operation OAEN1 Operational amplifier 1 operation control 0 Stops operational amplifier 1 operation 1 Enables ...

Page 359: ...ng ADP C4 ADP C3 ADP C2 ADP C1 ADP C0 ANI15 AVREFM P27 ANI11 P83 ANI10 AMP2 P82 ANI9 AMP2OUT P81 ANI8 AMP2 P80 ANI6 P26 ANI5 AMP1 P25 ANI4 AMP1OUT P24 ANI3 AMP1 P23 ANI2 AMP0 P22 ANI1 AMP0OUT P21 ANI0 AMP0 P20 0 0 0 0 0 A A A A A A A A A A A A 0 0 0 0 1 A A A A A A A A A A A D 0 0 0 1 0 A A A A A A A A A A D D 0 0 0 1 1 A A A A A A A A A D D D 0 0 1 0 0 A A A A A A A A D D D D 0 0 1 0 1 A A A A A ...

Page 360: ...ion If a pin is set as an analog input port not the pin level but 0 is always read Remark 78K0 KB2 A ANI0 to ANI5 ANI8 to ANI11 78K0 KC2 A ANI0 to ANI6 ANI8 to ANI11 ANI15 Figure 13 4 Format of Port Mode Registers 2 and 8 PM2 PM8 1 78K0 KB2 A Address FF22H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 PM25 PM24 PM23 PM22 PM21 PM20 Address FF28H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM8 1...

Page 361: ... select ANI Operational amplifier input Analog input selection Output mode Setting prohibited Table 13 3 Setting Functions of ANI1 AMP0OUT P21 ANI4 AMP1OUT P24 ANI9 AMP2OUT P81 Pins ADPC Register PM2 PM8 Register OAENn bit ADS Register ANI1 AMP0OUT P21 ANI4 AMP1OUT P24 ANI9 AMP2OUT P81 Pins 0 Digital input Input mode 1 Setting prohibited 0 Digital output Digital I O selection Output mode 1 Setting...

Page 362: ...t selection Output mode Setting prohibited Remark 78K0 KB2 A ANI11 P83 only 78K0 KC2 A ANI6 P26 ANI11 P83 Table 13 5 Setting Functions of ANI15 AVREFM P27 Pin 78K0 KC2 A only ADPC Register PM2 Register ADREF bit ADS Register ANI15 AVREFM P27 pin 0 Digital input Input mode 1 Setting prohibited 0 Digital output Digital I O selection Output mode 1 Setting prohibited Selects ANI Analog input to be con...

Page 363: ... amplifier mode is described below 1 Use the port mode register x PMx register to set the pins AMPn AMPn AMPnOUT to be used in single amplifier mode as input mode 2 Use the A D port configuration register ADPC to set the pins AMPn AMPn AMPnOUT to be used in single amplifier mode to analog input 3 Specify the operating mode by using the OAIM1 and OAIM0 bits of the operational amplifier control regi...

Page 364: ...us The functions of this mode are outlined below For details see 14 4 2 Asynchronous serial interface UART mode and 14 4 3 Dedicated baud rate generator Maximum transfer rate 625 kbps Two pin configuration TXD6 Transmit data output pin RXD6 Receive data input pin Data length of communication data can be selected from 7 or 8 bits Dedicated internal 8 bit baud rate generator allowing any baud rate t...

Page 365: ...r reception circuit may not be initialized 5 Set transmit data to TXB6 at least one base clock fXCLK6 after setting TXE6 1 6 If data is continuously transmitted the communication timing from the stop bit to the next start bit is extended two operating clocks of the macro However this does not affect the result of communication because the reception side initializes the timing when it has detected ...

Page 366: ...break field Sync field Identifier field Data field Data field Checksum field TX6 output INTST6Note 3 Notes 1 The wakeup signal frame is substituted by 80H transmission in the 8 bit mode 2 The sync break field is output by hardware The output width is the bit length set by bits 4 to 2 SBL62 to SBL60 of asynchronous serial interface control register 6 ASICL6 see 14 4 2 2 h SBF transmission 3 INTST6 ...

Page 367: ...vel data of less than 11 bits has been detected it is assumed that an SBF reception error has occurred The interrupt signal is not output and the SBF reception mode is restored 3 If SBF reception has been completed correctly an interrupt signal is output Start 16 bit timer event counter 00 by the SBF reception end interrupt servicing and measure the bit interval pulse width of the sync field see 6...

Page 368: ... port input switch control ISC0 ISC1 without connecting RXD6 and INTP0 TI000 externally Figure 14 3 Port Configuration for LIN Reception Operation RXD6 input INTP0 input TI000 input P11 RxD6 TI50Note 1 TO50Note 1 P120 INTP0 EXLVI P00 TI000Note 2 Port input switch control ISC0 ISC0 0 Select INTP0 P120 1 Select RxD6 P11 Port mode PM11 Output latch P11 Port mode PM120 Output latch P120 Port input swi...

Page 369: ... UART6 14 2 Configuration of Serial Interface UART6 Serial interface UART6 includes the following hardware Table 14 1 Configuration of Serial Interface UART6 Item Configuration Registers Receive buffer register 6 RXB6 Receive shift register 6 RXS6 Transmit buffer register 6 TXB6 Transmit shift register 6 TXS6 Control registers Asynchronous serial interface operation mode register 6 ASIM6 Asynchron...

Page 370: ... Filter INTSRE6 Asynchronous serial interface reception error status register 6 ASIS6 Asynchronous serial interface operation mode register 6 ASIM6 Asynchronous serial interface transmission status register 6 ASIF6 Transmission control Registers 8 Reception unit Transmission unit Clock selection register 6 CKSR6 Baud rate generator control register 6 BRGC6 Output latch P10 PM10 8 Selector TXD6 P10...

Page 371: ...mit buffer register 6 TXB6 This buffer register is used to set transmit data Transmission is started when data is written to TXB6 This register can be read or written by an 8 bit memory manipulation instruction Reset signal generation sets this register to FFH Cautions 1 Do not write data to TXB6 when bit 1 TXBF6 of asynchronous serial interface transmission status register 6 ASIF6 is 1 2 Do not r...

Page 372: ... TXE6 of ASIM6 1 or bits 7 and 5 POWER6 RXE6 of ASIM6 1 Figure 14 5 Format of Asynchronous Serial Interface Operation Mode Register 6 ASIM6 1 2 Address FF50H After reset 01H R W Symbol 7 6 5 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 Enables disables operation of internal operation clock 0 Note 1 Disables operation of the internal operation clock fixes the clock to low level a...

Page 373: ...ccur Cautions 1 To start the transmission set POWER6 to 1 and then set TXE6 to 1 To stop the transmission clear TXE6 to 0 and then clear POWER6 to 0 2 To start the reception set POWER6 to 1 and then set RXE6 to 1 To stop the reception clear RXE6 to 0 and then clear POWER6 to 0 3 Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RXD6 pin If POWER6 is set to 1 and RXE6 is set...

Page 374: ...SIS6 register is read 1 If the parity of transmit data does not match the parity bit on completion of reception FE6 Status flag indicating framing error 0 If POWER6 0 or RXE6 0 or if ASIS6 register is read 1 If the stop bit is not detected on completion of reception OVE6 Status flag indicating overrun error 0 If POWER6 0 or RXE6 0 or if ASIS6 register is read 1 If receive data is set to the RXB6 r...

Page 375: ...lag 0 If POWER6 0 or TXE6 0 or if the next data is not transferred from transmit buffer register 6 TXB6 after completion of transfer 1 If data is transferred from transmit buffer register 6 TXB6 if data transmission is in progress Cautions 1 To transmit data continuously write the first transmit data first byte to the TXB6 register Be sure to check that the TXBF6 flag is 0 If so write the next tra...

Page 376: ...at can be used for the peripheral hardware clock fPRS differs depending on the power supply voltage Supply Voltage Use frequency range of peripheral hardware clock fPRS 2 7 V VDD 5 5 V fPRS 20 MHz 1 8 V VDD 2 7 V fPRS 5 MHz The values shown in the table above are those when fPRS fXH XSEL 1 2 If the peripheral hardware clock fPRS operates on the internal high speed oscillation clock fRH XSEL 0 when...

Page 377: ...57H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of 8 bit counter 0 0 0 0 0 0 Setting prohibited 0 0 0 0 0 1 0 0 4 fXCLK6 4 0 0 0 0 0 1 0 1 5 fXCLK6 5 0 0 0 0 0 1 1 0 6 fXCLK6 6 1 1 1 1 1 1 0 0 252 fXCLK6 252 1 1 1 1 1 1 0 1 253 fXCLK6 253 1 1 1 1 1 1 1 0 254 fXCLK6 254 1 1 ...

Page 378: ... ASIM6 1 However do not set both SBRT6 and SBTT6 to 1 by a refresh operation during SBF reception SBRT6 1 or SBF transmission until INTST6 occurs since SBTT6 has been set 1 because it may re trigger SBF reception or SBF transmission Figure 14 10 Format of Asynchronous Serial Interface Control Register 6 ASICL6 1 2 Address FF58H After reset 16H R W Note Symbol 7 6 5 4 3 2 1 0 ASICL6 SBRF6 SBRT6 SBT...

Page 379: ... SBRT6 bit to 1 do not clear it to 0 before SBF reception is completed before an interrupt request signal is generated 3 The read value of the SBRT6 bit is always 0 SBRT6 is automatically cleared to 0 after SBF reception has been correctly completed 4 Before setting the SBTT6 bit to 1 make sure that bit 7 POWER6 and bit 6 TXE6 of ASIM6 1 After setting the SBTT6 bit to 1 do not clear it to 0 before...

Page 380: ... P00 78K0 KC2 A 1 RXD6 P11 ISC0 INTP0 input source selection 0 INTP0 P120 1 RXD6 P11 Note The assignment of pins used in serial interface CSI10 is set by ISC2 For details see CHAPTER 15 SERIAL INTERFACE CSI10 8 Port mode register 1 PM1 This register sets port 1 input output in 1 bit units When using the P10 TXD6 TI51 Note TO51 Note pin for serial interface data output clear PM10 to 0 and set the o...

Page 381: ...peration of internal operation clock 0 Note 1 Disables operation of the internal operation clock fixes the clock to low level and asynchronously resets the internal circuit Note 2 TXE6 Enables disables transmission 0 Disables transmission operation synchronously resets the transmission circuit RXE6 Enables disables reception 0 Disables reception synchronously resets the reception circuit Notes 1 I...

Page 382: ... register 6 BRGC6 Asynchronous serial interface control register 6 ASICL6 Input switch control register ISC Port mode register 1 PM1 Port register 1 P1 The basic procedure of setting an operation in the UART mode is as follows 1 Set the CKSR6 register see Figure 14 8 2 Set the BRGC6 register see Figure 14 9 3 Set bits 0 to 4 ISRM6 SL6 CL6 PS60 PS61 of the ASIM6 register see Figure 14 5 4 Set bits ...

Page 383: ...mission reception TXD6 RXD6 Notes 1 Can be set as port function or 8 bit timer 50 and 51 Note 2 2 78K0 KB2 A only Remark don t care POWER6 Bit 7 of asynchronous serial interface operation mode register 6 ASIM6 TXE6 Bit 6 of ASIM6 RXE6 Bit 5 of ASIM6 PM1 Port mode register P1 Port output latch 2 Communication operation a Format and waveform example of normal transmit receive data Figures 14 13 and ...

Page 384: ...rity Stop bit 1 or 2 bits The character bit length parity and stop bit length in one data frame are specified by asynchronous serial interface operation mode register 6 ASIM6 Whether data is communicated with the LSB or MSB first is specified by bit 1 DIR6 of asynchronous serial interface control register 6 ASICL6 Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 TXDLV6 of...

Page 385: ...p bit 1 bit Communication data 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3 Data length 8 bits MSB first Parity Even parity Stop bit 1 bit Communication data 55H TXD6 pin inverted output 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 4 Data length 7 bits LSB first Parity Odd parity Stop bit 2 bits Communication data 36H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 Parity Stop St...

Page 386: ...eption The number of bits that are 1 in the receive data including the parity bit is counted If it is odd a parity error occurs ii Odd parity Transmission Unlike even parity transmit data including the parity bit is controlled so that the number of bits that are 1 is odd If transmit data has an odd number of bits that are 1 0 If transmit data has an even number of bits that are 1 1 Reception The n...

Page 387: ...t register 6 TXS6 After that the transmit data is sequentially output from TXS6 to the TXD6 pin When transmission is completed the parity and stop bits set by ASIM6 are appended and a transmission completion interrupt request INTST6 is generated Transmission is stopped until the data to be transmitted next is written to TXB6 Figure 14 15 shows the timing of the transmission completion interrupt re...

Page 388: ... is use in LIN communication operation the continuous transmission function cannot be used Make sure that asynchronous serial interface transmission status register 6 ASIF6 is 00H before writing transmit data to transmit buffer register 6 TXB6 TXBF6 Writing to TXB6 Register 0 Writing enabled 1 Writing disabled Caution To transmit data continuously write the first transmit data first byte to the TX...

Page 389: ...nsfer executed necessary number of times Yes Read ASIF6 TXBF6 0 No No Yes Transmission completion interrupt occurs Read ASIF6 TXSF6 0 No No No Yes Yes Yes Yes Completion of transmission processing Transfer executed necessary number of times Remark TXB6 Transmit buffer register 6 ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 transmit buffer data flag TXSF6 ...

Page 390: ...a 1 Data 2 Data 3 Data 2 Data 1 Data 3 FF FF Parity Stop Data 2 Parity Stop TXB6 TXS6 TXBF6 TXSF6 Start Start Note Note When ASIF6 is read there is a period in which TXBF6 and TXSF6 1 1 Therefore judge whether writing is enabled using only the TXBF6 bit Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous seri...

Page 391: ...B6 TXS6 TXBF6 TXSF6 POWER6 or TXE6 Start Remark TXD6 TXD6 pin output INTST6 Interrupt request signal TXB6 Transmit buffer register 6 TXS6 Transmit shift register 6 ASIF6 Asynchronous serial interface transmission status register 6 TXBF6 Bit 1 of ASIF6 TXSF6 Bit 0 of ASIF6 POWER6 Bit 7 of asynchronous serial interface operation mode register ASIM6 TXE6 Bit 6 of asynchronous serial interface operati...

Page 392: ... bit has been received the reception completion interrupt INTSR6 is generated and the data of RXS6 is written to receive buffer register 6 RXB6 If an overrun error OVE6 occurs however the receive data is not written to RXB6 Even if a parity error PE6 occurs while reception is in progress reception continues to the reception position of the stop bit and a reception error interrupt INTSR6 INTSRE6 is...

Page 393: ... Error Cause Parity error The parity specified for transmission does not match the parity of the receive data Framing error Stop bit is not detected Overrun error Reception of the next data is completed before data is read from receive buffer register 6 RXB6 The reception error interrupt can be separated into reception completion interrupt INTSR6 and error interrupt INTSRE6 by clearing bit 0 ISRM6...

Page 394: ...Transmission Operation When bit 7 POWER6 of asynchronous serial interface mode register 6 ASIM6 is set to 1 the TXD6 pin outputs high level Next when bit 6 TXE6 of ASIM6 is set to 1 the transmission enabled status is entered and SBF transmission is started by setting bit 5 SBTT6 of asynchronous serial interface control register 6 ASICL6 to 1 Thereafter a low level of bits 13 to 20 set by bits 4 to...

Page 395: ...pt request INTSR6 is generated as normal processing At this time the SBRF6 and SBRT6 bits are automatically cleared and SBF reception ends Detection of errors such as OVE6 PE6 and FE6 bits 0 to 2 of asynchronous serial interface reception error status register 6 ASIS6 is suppressed and error detection processing of UART communication is not performed In addition data transfer between receive shift...

Page 396: ...n POWER6 0 Transmission counter This counter stops operation cleared to 0 when bit 7 POWER6 or bit 6 TXE6 of asynchronous serial interface operation mode register 6 ASIM6 is 0 It starts counting when POWER6 1 and TXE6 1 The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 TXB6 If data are continuously transmitted the counter is cleared to 0 again whe...

Page 397: ... register 6 BRGC6 Baud rate generator control register 6 2 Generation of serial clock A serial clock to be generated can be specified by using clock selection register 6 CKSR6 and baud rate generator control register 6 BRGC6 The clock to be input to the 8 bit counter can be set by bits 3 to 0 TPS63 to TPS60 of CKSR6 and the division value fXCLK6 4 to fXCLK6 255 of the 8 bit counter can be set by b...

Page 398: ...ting prohibited Notes 1 The frequency that can be used for the peripheral hardware clock fPRS differs depending on the power supply voltage Supply Voltage Use frequency range of peripheral hardware clock fPRS 2 7 V VDD 5 5 V fPRS 20 MHz 1 8 V VDD 2 7 V fPRS 5 MHz The values shown in the table above are those when fPRS fXH XSEL 1 2 If the peripheral hardware clock fPRS operates on the internal high...

Page 399: ... 13 1202 0 16 5H 65 1202 0 16 6H 65 1202 0 16 7H 65 1202 0 16 2400 5H 13 2404 0 16 4H 65 2404 0 16 5H 65 2404 0 16 6H 65 2404 0 16 4800 4H 13 4808 0 16 3H 65 4808 0 16 4H 65 4808 0 16 5H 65 4808 0 16 9600 3H 13 9615 0 16 2H 65 9615 0 16 3H 65 9615 0 16 4H 65 9615 0 16 19200 2H 13 19231 0 16 1H 65 19231 0 16 2H 65 19231 0 16 3H 65 19231 0 16 24000 1H 21 23810 0 79 3H 13 24038 0 16 4H 13 24038 0 16 ...

Page 400: ...it Bit 0 Bit 1 Bit 7 Parity bit Minimum permissible data frame length Maximum permissible data frame length Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Latch timing Stop bit Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit As shown in Figure 14 25 the latch timing of the receive data is determined by the counter set by baud rate generator control register 6 BRGC6 after the start bit has been de...

Page 401: ...te error between UART6 and the transmission destination can be calculated from the above minimum and maximum baud rate expressions as follows Table 14 6 Maximum Minimum Permissible Baud Rate Error Division Ratio k Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error 4 2 33 2 44 8 3 53 3 61 20 4 26 4 31 50 4 56 4 58 100 4 66 4 67 255 4 72 4 73 Remarks 1 The permissible error of r...

Page 402: ...because the timing is initialized on the reception side when the start bit is detected Figure 14 26 Data Frame Length During Continuous Transmission Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame FL FL FL FL FL FL FLstp Start bit of second byte Start bit Bit 0 Where the 1 bit data length is FL the stop bit length is FLstp and base clock frequency is fXCLK6 the following expression...

Page 403: ... and reception can be simultaneously executed In addition whether 8 bit data is communicated with the MSB or LSB first can be specified so this interface can be connected to any device The 3 wire serial I O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface For details see 15 4 2 3 wire serial I O mode Caution The pins to which the serial clock SCK10...

Page 404: ... INTCSI10 SI10 P32 INTP4 OCD1BNote 1 fPRS 2 fPRS 22 fPRS 23 fPRS 24 fPRS 25 fPRS 26 fPRS 27 SSI10 PM35 PM31 SCK10 P31 INTP5 OCD1ANote 1 SSI10Note 2 Internal bus Transmit buffer register 10 SOTB10 Serial I O shift register 10 SIO10 Output selector SO10 output Output latch P35 Output latch Transmit data controller Output latch P31Note 1 Note 1 Note 2 Transmit controller Clock start stop controller c...

Page 405: ...is started when data is written to SOTB11 with a low level input to the SSI10 pin For details on the transmission reception operation refer to 15 4 2 2 Communication operation 2 Serial I O shift register 10 SIO10 This is an 8 bit register that converts data from parallel data into serial data and vice versa This register can be read by an 8 bit memory manipulation instruction Reception is started ...

Page 406: ...M10 Serial clock selection register 10 CSIC10 Input switch control register ISC Port mode register 3 4Note 6 PM3 PM4Note PM6 Port register 3 4Note 6 P3 P4Note P6 Note 78K0 KC2 A only 1 Serial operation mode register 10 CSIM10 CSIM10 is used to select the operation mode and enable or disable operation CSIM10 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clea...

Page 407: ...ed DIR10 Note 9 First bit specification 0 MSB 1 LSB CSOT10 Communication status flag 0 Communication is stopped 1 Communication is in progress Notes 1 Bit 0 is a read only bit 2 78K0 KC2 A only 3 To use P60 SCK10 SCLA0 P31 INTP5 OCD1A SCK10 and P35 SO10 INTP1 as general purpose ports set CSIM10 in the default status 00H 4 Bit 0 CSOT10 of CSIM10 and serial I O shift register 10 SIO10 are reset 5 Do...

Page 408: ...6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 3 1 1 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 SI10 input timing 4 CSI10 serial clock selection Notes 1 2 CKS102 CKS101 CKS100 fPRS 2 MHz fPRS 5 MHz fPRS 10 MHz fPRS 20 MHz Mode 0 0 0 fPRS 2 1 MHz 2 5 MHz 5 MHz Setting prohibited 0 0 1 fPR...

Page 409: ... 2 7 V VDD 4 0 V Serial clock 4 MHz 1 8 V VDD 2 7 V Serial clock 2 MHz 3 Do not start communication operation with the external clock from SCK10 when the internal high speed oscillation clock and high speed system clock are stopped while the CPU operates with the subsystem clock or when in the STOP mode 4 When clear the bit 2 ISC2 of the Input switch control register ISC to 0 to select the master ...

Page 410: ...smission reception Slave transmission reception Note ISC0 and ISC1 are setting about serial interface UART6 refer to CHAPTER 14 SERIAL INTERFACE UART6 4 Port mode registers 3 4Note 1 6 PM3 PM4 Note 1 PM6 This register sets port 3 4 and 6 input output in 1 bit units When using P31 INTP5 OCD1A SCK10 as the clock output pin of the serial interface clear PM31 to 0 and set the output latches of P31 to ...

Page 411: ... the format of port mode register 3 of 78K0 KC2 A see 1 Port mode registers PMxx in 4 3 Registers Controlling Port Function Figure 15 6 Format of Port Mode Register 4 PM4 78K0 KC2 A Address FF24H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PM4 1 1 1 1 1 PM42 PM41 PM40 PM4n P4n pin I O mode selection n 0 to 2 0 Output mode output buffer on 1 Input mode output buffer off Figure 15 7 Format of Port Mo...

Page 412: ... serial operation mode register 10 CSIM10 To set the operation stop mode clear bit 7 CSIE10 of CSIM10 to 0 a Serial operation mode register 10 CSIM10 CSIM10 can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears CSIM10 to 00H Address FF80H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 SSE10 DIR10 0 0 0 CSOT10 CSIE10 Operation control in 3 wi...

Page 413: ...4Note 6 P3 P4 Note P6 The basic procedure of setting an operation in the 3 wire serial I O mode is as follows 1 Set the bit 2 ISC2 of the input switch register ISC 2 Set the CSIC10 register see Figures 15 3 3 Set bits 4 to 6 DIR10 SSE10Note TRMD10 of the CSIM10 register see Figures 15 2 4 Set bit 7 CSIE10 of the CSIM10 register to 1 Transmission reception is enabled 5 Write data to transmit buffer...

Page 414: ... 2 INTP9 PCL P42 1 0 1 1 Note 2 Note 2 1 1 Slave recepti on Note 5 SI10 INTP1 P35Note 3 SCK10 Input Note 5 SSI11 0 Note 2 Note 2 INTP9 PCL P42 1 1 1 Note 2 Note 2 0 0 1 1 Slave transm ission Note 5 P61 P32 SO10 SCK10 Input Note 5 SSI11 0 Note 2 Note 2 INTP9 PCL P42 1 1 1 1 0 0 1 1 Slave transm ission Note 5 SI10 SO10 SCK10 Input Note 5 SSI11 1 0 0 1 Note 2 Note 2 0 1 Note 2 Note 2 Master recepti o...

Page 415: ...0 5 To use the slave mode set CKS102 CKS101 and CKS100 to 1 1 1 6 To use the master mode set bit 2 ISC2 of the input switch control register ISC to 1 Remark don t care CSIE10 Bit 7 of serial operation mode register 10 CSIM10 TRMD10 Bit 6 of CSIM10 CKP10 Bit 4 of serial clock selection register 10 CSIC10 CKS102 CKS101 CKS100 Bits 2 to 0 of CSIC10 PMx Port mode register Px Port output latch The func...

Page 416: ...d when SIO10 is read 2 High level input to the SSI10 pin Transmission reception or reception is held therefore even if SOTB10 is written or SIO10 is read transmission reception or reception will not be started 3 Data is written to SOTB10 or data is read from SIO10 while a high level is input to the SSI10 pin then a low level is input to the SSI10 pin Transmission reception or reception is started ...

Page 417: ...timing Type 1 TRMD10 1 DIR10 0 CKP10 0 DAP10 0 SSE10 1Note ABH 56H ADH 5AH B5H 6AH D5H AAH SCK10 SSI10 Read write trigger SOTB10 SIO10 CSOT10 INTCSI10 CSIIF10 SI10 receive AAH SO10 55H communication data 55H is written to SOTB10 Note Note The SSE10 flag and SSI10 pins are only mounted on 78K0 KC2 A only These pins are used in the slave mode ...

Page 418: ... timing Type 2 TRMD10 1 DIR10 0 CKP10 0 DAP10 1 SSE10 1Note ABH 56H ADH 5AH B5H 6AH D5H AAH SCK10 Read write trigger SOTB10 SIO10 CSOT10 INTCSI10 CSIIF10 SI10 input AAH SO10 SSI10Note 55H communication data 55H is written to SOTB10 Note The SSE10 flag and SSI10 pins are only mounted on 78K0 KC2 A only These pins are used in the slave mode ...

Page 419: ...D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 Writing to SOTB10 or reading from SIO10 SI10 capture CSIIF10 CSOT10 c Type 3 CKP10 1 DAP10 0 DIR10 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 Writing to SOTB10 or reading from SIO10 SI10 capture CSIIF10 CSOT10 d Type 4 CKP10 1 DAP10 1 DIR10 0 D7 D6 D5 D4 D3 D2 D1 D0 SCK10 SO10 Writing to SOTB10 or reading from SIO10 SI10 capture CSIIF10 CSOT10 Remark The above figure illu...

Page 420: ... 0 SCK10 SOTB10 SIO10 Output latch SO10 Writing to SOTB10 or reading from SIO10 First bit 2nd bit The first bit is directly latched by the SOTB10 register to the output latch at the falling or rising edge of SCK10 and output from the SO10 pin via an output selector Then the value of the SOTB10 register is transferred to the SIO10 register at the next rising or falling edge of SCK10 and shifted one...

Page 421: ... latched by the SOTB10 register at the falling edge of the write signal of the SOTB10 register or the read signal of the SIO10 register and output from the SO10 pin via an output selector Then the value of the SOTB10 register is transferred to the SIO10 register at the next falling or rising edge of SCK10 and shifted one bit At the same time the first bit of the receive data is stored in the SIO10...

Page 422: ...olds the output value of the last bit Figure 15 11 Output Value of SO10 Pin Last Bit 1 2 a Type 1 CKP10 0 DAP10 0 SCK10 SOTB10 SIO10 SO10 Writing to SOTB10 or reading from SIO10 Next request is issued Last bit Output latch b Type 3 CKP10 1 DAP10 0 Last bit Next request is issued SCK10 SOTB10 SIO10 Output latch SO10 Writing to SOTB10 or reading from SIO10 ...

Page 423: ... of SO10 Pin Last Bit 2 2 c Type 2 CKP10 0 DAP10 1 SCK10 SOTB10 SIO10 SO10 Last bit Writing to SOTB10 or reading from SIO10 Next request is issued Output latch d Type 4 CKP10 1 DAP10 1 Last bit Next request is issued SCK10 SOTB10 SIO10 Output latch SO10 Writing to SOTB10 or reading from SIO10 ...

Page 424: ...DAP10 1 DIR 10 1 Value of bit 0 of SOTB10 TRMD10 0 Note 3 Outputs low leve CSIE10 1 TRMD10 1 Transmit data Note 4 Notes 1 The actual output of the SO10 INTP1 P35 pin is determined according to PM35 and P35 as well as the SO10 output 2 Status after reset 3 To use P35 SO10 INTP1 as general purpose port set the serial clock selection register 10 CSIC10 in the default status 00H 4 After transmission h...

Page 425: ...evice can generated start condition address transfer direction specification data and stop condition data to the slave device via the serial data bus The slave device automatically detects these received status and data by hardware This function can simplify the part of application program that controls the I2 C bus Since the SCLA0 and SDAA0 pins are used for open drain outputs IICA requires pull ...

Page 426: ...al IICA shift register IICA SO latch Set Clear IICWL TRC0 DFC Data hold time correction circuit Start condition generator Stop condition generator ACK generator Wakeup controller N ch open drain output PM61 Noise eliminator Bus status detector ACK detector Stop condition detector Serial clock counter Interrupt request signal generator Serial clock controller Serial clock wait controller Start cond...

Page 427: ...figuration example Figure 16 2 Serial Bus Configuration Example Using I2 C Bus Master CPU1 Slave CPU1 Address 0 SDAA0 SCLA0 Serial data bus Serial clock VDD VDD SDAA0 SCLA0 SDAA0 SCLA0 SDAA0 SCLA0 SDAA0 SCLA0 Master CPU2 Slave CPU2 Address 1 Slave CPU3 Address 2 Slave IC Address 3 Slave IC Address N ...

Page 428: ...o IICA Cancel the wait state and start data transfer by writing data to IICA during the wait period IICA can be set by an 8 bit memory manipulation instruction Reset signal generation clears IICA to 00H Figure 16 3 Format of IICA Shift Register IICA Symbol IICA Address FFA6H After reset 00H R W 7 6 5 4 3 2 1 0 Cautions 1 Do not write data to IICA during data transfer 2 Write or read IICA only duri...

Page 429: ...request generated when a stop condition is detected set by SPIE0 bit Remark WTIM0 bit Bit 3 of IICA control register 0 IICACTL0 SPIE0 bit Bit 4 of IICA control register 0 IICACTL0 7 Serial clock controller In master mode this circuit generates the clock output via the SCLA0 pin from a sampling clock 8 Serial clock wait controller This circuit controls the wait timing 9 ACK generator stop condition...

Page 430: ...the bus status cannot be detected immediately following operation the initial status is set by the STCEN bit Remark STT0 bit Bit 1 of IICA control register 0 IICACTL0 SPT0 bit Bit 0 of IICA control register 0 IICACTL0 IICRSV bit Bit 0 of IICA flag register 0 IICAF0 IICBSY bit Bit 6 of IICA flag register 0 IICAF0 STCF bit Bit 7 of IICA flag register 0 IICAF0 STCEN bit Bit 1 of IICA flag register 0 ...

Page 431: ...tting register IICWL IICA high level width setting register IICWH Port mode register 6 PM6 Port register 6 P6 1 IICA control register 0 IICACTL0 This register is used to enable stop I2 C operations set wait timing and set other I 2 C operations IICACTL0 can be set by a 1 bit or 8 bit memory manipulation instruction However set the SPIE0 WTIM0 and ACKE0 bits while IICE0 bit 0 or during the wait per...

Page 432: ...ations remains in effect until the following communications entry conditions are met After a stop condition is detected restart is in master mode An address match or extension code reception occurs after the start condition Condition for clearing LREL0 0 Condition for setting LREL0 1 Automatically cleared after execution Reset Set by instruction WREL0 Note 2 Wait cancellation 0 Do not cancel wait ...

Page 433: ...h clock during address transfer independently of the setting of this bit The setting of this bit is valid when the address transfer is completed When in master mode a wait is inserted at the falling edge of the ninth clock during address transfers For a slave device that has received a local address a wait is inserted at the falling edge of the ninth clock after an acknowledge ACK is issued Howeve...

Page 434: ...en master device Generates a restart condition after releasing the wait Cautions concerning set timing For master reception Cannot be set to 1 during transfer Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been notified of final reception For master transmission A start condition cannot be generated normally during the acknowledge period Set to 1 during t...

Page 435: ...When WTIM0 has been cleared to 0 if SPT0 is set to 1 during the wait period that follows output of eight clocks note that a stop condition will be generated during the high level period of the ninth clock WTIM0 should be changed from 0 to 1 during the wait period following the output of eight clocks and SPT0 should be set to 1 during the wait period that follows the output of the ninth clock Setti...

Page 436: ... STD0 SPD0 MSTS0 Master device status 0 Slave device status or communication standby status 1 Master device communication status Condition for clearing MSTS0 0 Condition for setting MSTS0 1 When a stop condition is detected When ALD0 1 arbitration loss Cleared by LREL0 1 exit from communications When IICE0 changes from 1 to 0 operation stop Reset When a start condition is generated ALD0 Detection ...

Page 437: ...r than transmit status The SDAA0 line is set for high impedance 1 Transmit status The value in the SO0 latch is enabled for output to the SDAA0 line valid starting at the falling edge of the first byte s ninth clock Condition for clearing TRC0 0 Condition for setting TRC0 1 Both master and slave When a stop condition is detected Cleared by LREL0 1 exit from communications When IICE0 changes from 1...

Page 438: ...ondition is detected SPD0 Detection of stop condition 0 Stop condition was not detected 1 Stop condition was detected The master device s communication is terminated and the bus is released Condition for clearing SPD0 0 Condition for setting SPD0 1 At the rising edge of the address transfer byte s first clock following setting of this bit and detection of a start condition When IICE0 changes from ...

Page 439: ...struction Detection of start condition Reset Condition for setting STCEN 1 Set by instruction STCEN 0 1 After operation is enabled IICE0 1 enable generation of a start condition upon detection of a stop condition After operation is enabled IICE0 1 enable generation of a start condition without detecting a stop condition Initial start enable trigger Condition for clearing IICRSV 0 Cleared by instru...

Page 440: ...t be written after WUP has been cleared 0 The interrupt timing when the address has matched or when an extension code has been received while WUP 1 is identical to the interrupt timing when WUP 0 A delay of the difference of sampling by the clock will occur Furthermore when WUP 1 a stop condition interrupt is not generated even if the SPIE0 bit is set to 1 When WUP 0 is set by a source other than ...

Page 441: ...dard mode 1 Operates in fast mode DFC0 Digital filter operation control 0 Digital filter off 1 Digital filter on Digital filter can be used only in fast mode In fast mode the transfer clock does not vary regardless of the DFC0 bit being set 1 or cleared 0 The digital filter is used for noise elimination in fast mode Notes 1 Bits 4 and 5 are read only 2 The status of IICAS0 must be checked and WUP ...

Page 442: ...idth tHIGH of the SCLA0 pin signal that is output by serial interface IICA being in master mode This register can be set by an 8 bit memory manipulation instruction Set IICWH while bit 7 IICE of IICA control register 0 IICACTL0 is 0 Reset signal generation sets this register to FFH See the 16 4 2 Setting transfer clock by using IICWL and IICWH registers for how to set the IICWL Figure 16 10 Format...

Page 443: ...U19780EJ2V0UD 441 Figure 16 11 Format of Port Mode Register 6 PM6 PM60 PM61 1 1 1 1 1 1 P6n pin I O mode selection n 0 1 Output mode output buffer on Input mode output buffer off PM6n 0 1 0 1 2 3 4 5 6 7 PM6 Address FF26H After reset FFH R W Symbol ...

Page 444: ...ices Input is Schmitt input 2 SDAA0 This pin is used for serial data input and output This pin is an N ch open drain output for both master and slave devices Input is Schmitt input Since outputs from the serial clock line and the serial data bus line are N ch open drain outputs an external pull up resistor is required Figure 16 12 Pin Configuration Diagram Master device Clock output Clock input Da...

Page 445: ...e rounded up When the fast mode IICWL 0 52 Transfer clock fPRS IICWH 0 48 Transfer clock tR tF fPRS When the normal mode IICWL 0 47 Transfer clock fPRS IICWH 0 53 Transfer clock tR tF fPRS Remark The data hold time is calculated as follows based on the setting of the IICWL register Data hold time Higher 6 bit of IICWL fPRS Example If the transfer clock is 400 kHz fast mode fPRS is 20 MHz and IICWL...

Page 446: ...m fPRS operation frequency when setting the transfer clock The minimum fPRS operation frequency for serial interface IICA is determined according to the mode Fast mode fPRS 3 5 MHz min Normal mode fPRS 1 MHz min Remark IICWL IICA low level width setting register IICWH IICA high level width setting register tF SDAA0 and SCLA0 signal falling times refer to CHAPTER 28 ELECTRIC SPECIFICTION tR SDAA0 a...

Page 447: ...rmally it is output by the device that receives 8 bit data The serial clock SCLA0 is continuously output by the master device However in the slave device the SCLA0 s low level period can be extended and a wait can be inserted 16 5 1 Start conditions A start condition is met when the SCLA0 pin is at high level and the SDAA0 pin changes from high level to low level The start conditions for the SCLA0...

Page 448: ...if data other than a local address or extension code is received during slave device operation Addresses are output when a total of 8 bits consisting of the slave address and the transfer direction described in 16 5 3 Transfer direction specification are written to the IICA shift register IICA The received addresses are written to IICA The slave address is assigned to the higher 7 bits of IICA 16 ...

Page 449: ... Bit 3 TRC0 of the IICAS0 register is set by the data of the eighth bit that follows 7 bit address information Usually set ACKE0 to 1 for reception TRC0 0 If a slave can receive no more data during reception TRC0 0 or does not require the next data item then the slave must inform the master by clearing ACKE0 to 0 that it will not receive any more data When the master does not require the next data...

Page 450: ...er device generates to the slave device when serial transfer has been completed When the device is used as a slave stop conditions can be detected Figure 16 18 Stop Condition SCLA0 SDAA0 H A stop condition is generated when bit 0 SPT0 of IICA control register 0 IICACTL0 is set to 1 When the stop condition is detected bit 0 SPD0 of the IICA status register 0 IICAS0 is set to 1 and INTIICA0 is gener...

Page 451: ...nd slave devices the next data transfer can begin Figure 16 19 Wait 1 2 1 When master device has a nine clock wait and slave device has an eight clock wait master transmits slave receives and ACKE0 1 Master IICA SCLA0 Slave IICA SCLA0 ACKE0 Transfer lines SCLA0 SDAA0 6 7 8 9 1 2 3 Master returns to high impedance but slave is in wait state low level Wait after output of ninth clock IICA data write...

Page 452: ...0 ACK D7 D6 D5 Generate according to previously set ACKE0 value Remark ACKE0 Bit 2 of IICA control register 0 IICACTL0 WREL0 Bit 5 of IICA control register 0 IICACTL0 A wait may be automatically generated depending on the setting of bit 3 WTIM0 of IICA control register 0 IICACTL0 Normally the receiving side cancels the wait state when bit 5 WREL0 of IICACTL0 is set to 1 or when FFH is written to t...

Page 453: ...er 0 IICACTL0 to 1 To generate a restart condition after canceling a wait state set bit 1 STT0 of IICACTL0 to 1 To generate a stop condition after canceling a wait state set bit 0 SPT0 of IICACTL0 to 1 Execute the canceling processing only once for one wait state If for example data is written to IICA after canceling a wait state by setting WREL0 to 1 an incorrect value may be output to SDAA0 beca...

Page 454: ...d extension code is not received neither INTIICA0 nor a wait occurs Remark The numbers in the table indicate the number of the serial clock s clock signals Interrupt requests and wait control are both synchronized with the falling edge of these clock signals 1 During address transmission reception Slave device operation Interrupt and wait timing are determined depending on the conditions described...

Page 455: ...e slave address register 0 SVA0 is not affected 2 If 11110 0 is set to SVA0 by a 10 bit address transfer and 11110 0 is transferred from the master device the results are as follows Note that INTIICA0 occurs at the falling edge of the eighth clock Higher four bits of data match EXC0 1 Seven bits of data match COI0 1 Remark EXC0 Bit 5 of IICA status register 0 IICAS0 COI0 Bit 4 of IICA status regis...

Page 456: ...the timing by which the arbitration loss occurred and the SCLA0 and SDAA0 lines are both set to high impedance which releases the bus The arbitration loss is detected based on the timing of the next interrupt request the eighth or ninth clock when a stop condition is detected etc and the ALD0 1 setting that has been made by software For details of interrupt request timing see 16 5 8 Interrupt requ...

Page 457: ... level while attempting to generate a restart condition At falling edge of eighth or ninth clock following byte transfer Note 1 When stop condition is detected while attempting to generate a restart condition When stop condition is generated when SPIE0 1 Note 2 When data is at low level while attempting to generate a stop condition When SCLA0 is at low level while attempting to generate a restart ...

Page 458: ... to a slave device However when a stop condition is detected bit 4 SPIE0 of IICA control register 0 IICACTL0 is set regardless of the wakeup function and this determines whether interrupt requests are enabled or disabled To use the wakeup function in the STOP mode set WUP to 1 Addresses can be received regardless of the operation clock An interrupt request signal INTIICA0 is also generated when a ...

Page 459: ...ing Extension Code Reception Waits for 5 clocks Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA STOP mode state No Yes WUP 0 Wait Reading IICAS0 INTIICA0 1 Note Note Perform the processing after INTIICA0 1 also when an INTIICA0 vector interrupt occurs ...

Page 460: ... as Master After STOP Mode Is Released by Other Than INTIICA0 Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA No Yes Releases STOP mode by an interrupt other than INTIICA0 START WUP 1 SPIE0 1 Releasing STOP mode Reading IICAS0 STOP instruction STOP mode state Waits for 3 clocks Wait INTIICA0 1 Note WUP 0 STOP condition i...

Page 461: ...responding to the operation to be executed after checking the operation state of serial interface IICA No Yes Releases STOP mode by an interrupt other than INTIICA0 START WUP 1 SPIE0 1 Releasing STOP mode Reading IICAS0 Interrupt servicing STOP instruction STOP mode state Waits for 3 clocks Wait INTIICA0 1 Note WUP 0 Waits for 5 clocks Wait Select as slave Note INTIICA0 is set to 1 even if a STOP ...

Page 462: ...IICACTL0 was set to 1 and it was detected by generation of an interrupt request signal INTIICA0 that the bus was released detection of the stop condition then the device automatically starts communication as the master Data written to IICA before the stop condition is detected is invalid When STT0 has been set to 1 the operation mode as start condition or as communication reservation is determined...

Page 463: ...A control register 0 IICACTL0 STD0 Bit 1 of IICA status register 0 IICAS0 SPD0 Bit 0 of IICA status register 0 IICAS0 Communication reservations are accepted via the timing shown in Figure 16 26 After bit 1 STD0 of the IICA status register 0 IICAS0 is set to 1 a communication reservation can be made by setting bit 1 STT0 of IICA control register 0 IICCATL0 to 1 before a stop condition is detected ...

Page 464: ...e Confirmation of communication reservation Clear user flag IICA write operation Notes 1 The wait time is calculated as follows IICWL setting value IICWH setting value 4 tF 2 fPRS clocks 2 The communication reservation operation executes a write to the IICA shift register IICA when a stop condition interrupt request occurs Remark STT0 Bit 1 of IICA control register 0 IICACTL0 MSTS0 Bit 7 of IICA s...

Page 465: ...n is not generated The following two statuses are included in the status where bus is not used When arbitration results in neither master nor slave operation When an extension code is received and slave operation is disabled ACK is not returned and the bus was released by setting bit 6 LREL0 of IICACTL0 to 1 and saving communication To confirm whether the start condition was generated or request w...

Page 466: ...I2 C operation is enabled and the device participates in communication already in progress when the SDAA0 pin is low and the SCLA0 pin is high the macro of I 2 C recognizes that the SDA0 pin has gone low detects a start condition If the value on the bus at this time can be recognized as an extension code ACK is returned but this interferes with other I2 C communications To avoid this start I 2 C i...

Page 467: ...leased state This flowchart is broadly divided into the initial settings communication waiting and communication processing The processing when the 78K0R IE3 looses in arbitration and is specified as the slave is omitted here and only the processing as the master is shown Execute the initial settings at startup to take part in a communication Then wait for the communication request as the master o...

Page 468: ...t mode register 6 PM6 Sets a transfer clock Sets a local address Sets a start condition Prepares for starting communication generates a start condition Starts communication specifies an address and transfer direction Waits for detection of acknowledge Waits for data transmission Starts transmission Communication processing Initial setting Starts reception Waits for data reception INTIICA0 interrup...

Page 469: ...ion generates a stop condition Waits for detection of the stop condition No Yes Yes No INTIICA0 interrupt occurs INTIICA0 interrupt occurs Yes No Yes No SPD0 1 Yes No Slave operation No INTIICA0 interrupt occurs Yes No 1 B SPIE0 0 Yes No Waits for a communication request Waits for a communication Initial setting IICACTL0 1XX111XXB IICE0 1 IICACTL0 0XX111XXB ACKE0 WTIM0 SPIE0 1 Setting of the port ...

Page 470: ...No No A C STT0 1 WaitNote Slave operation Yes IICBSY 0 EXC0 1 or COI0 1 Prepares for starting communication generates a start condition Disables reserving communication Enables reserving communication Waits for bus release Detects a stop condition No No INTIICA0 interrupt occurs Yes Yes No Yes STCF 0 No B D C D Communication processing Communication processing Note The wait time is calculated as f...

Page 471: ...occurs No Yes ACKD0 1 No Yes No C 2 Yes MSTS0 1 No Yes Transfer end No Yes ACKD0 1 No 2 Yes MSTS0 1 No 2 Waits for detection of ACK Yes No INTIICA0 interrupt occurs Yes MSTS0 1 No C 2 Yes EXC0 1 or COI0 1 No 1 2 SPT0 1 STT0 1 Slave operation END Communication processing Communication processing Remarks 1 Conform to the specifications of the product that is communicating with respect to the transmi...

Page 472: ...gs and passing them to the main processing instead of INTIICA0 1 Communication mode flag This flag indicates the following two communication statuses Clear mode Status in which data communication is not performed Communication mode Status in which data communication is performed from valid address detection to stop condition detection no detection of ACK from master address mismatch 2 Ready flag T...

Page 473: ...es Yes Yes Yes No No No No No No WREL0 1 ACKD0 1 No Yes No Yes No START Communication mode flag 1 Communication mode flag 1 Communication direction flag 1 Ready flag 1 Communication direction flag 0 Reading IICA Clearing ready flag Clearing ready flag Communication direction flag 1 Clearing communication mode flag WREL0 1 Writing IICA SVA0 XXH Sets a local address IICWL IICWH XXH Selects a transfe...

Page 474: ...s not match If the address matches the communication mode is set wait is cancelled and processing returns from the interrupt the ready flag is cleared 3 For data transmit receive only the ready flag is set Processing returns from the interrupt with the I2 C bus remaining in the wait state Remark 1 to 3 above correspond to 1 to 3 in Figure 16 31 Slave Operation Flowchart 2 Figure 16 31 Slave Operat...

Page 475: ...rence The timing of transmitting or receiving data and generation of interrupt request signal INTIICA0 and the value of the IICAS0 register when the INTIICA0 signal is generated are shown below Remark ST Start condition AD6 to AD0 Address R W Transfer direction specification ACK Acknowledge D7 to D0 Data SP Stop condition ...

Page 476: ...TIM0 to 1 Note 4 IICAS0 1000 00B Sets SPT0 to 1 Note 5 IICAS0 00000001B Note To generate a stop condition set WTIM0 to 1 and change the timing for generating the INTIICA0 interrupt request signal Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP SPT0 1 3 4 2 1 1 IICAS0 1000 110B 2 IICAS0 1000 100B 3 IICAS0 1000 00B Set...

Page 477: ...1B Notes 1 To generate a start condition set WTIM0 to 1 and change the timing for generating the INTIICA0 interrupt request signal 2 Clear WTIM0 to 0 to restore the original setting 3 To generate a stop condition set WTIM0 to 1 and change the timing for generating the INTIICA0 interrupt request signal Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ...

Page 478: ...Note 4 IICAS0 1010 00B Sets SPT0 to 1 5 IICAS0 00000001B Note To generate a stop condition set WTIM0 to 1 and change the timing for generating the INTIICA0 interrupt request signal Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP SPT0 1 3 4 2 1 1 IICAS0 1010 110B 2 IICAS0 1010 100B 3 IICAS0 1010 00B Sets SPT0 to 1 4 I...

Page 479: ...D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 1 IICAS0 0001 110B 2 IICAS0 0001 000B 3 IICAS0 0001 000B 4 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 1 IICAS0 0001 110B 2 IICAS0 0001 100B 3 IICAS0 0001 00B 4 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ...

Page 480: ... IICAS0 0001 110B 2 IICAS0 0001 000B 3 IICAS0 0001 110B 4 IICAS0 0001 000B 5 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart matches with SVA0 ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 5 2 1 1 IICAS0 0001 110B 2 IICAS0 0001 00B 3 IICAS0 0001 110B 4 IICAS0 0001 00B 5 IICAS0 00000001B Remark Always gener...

Page 481: ... 110B 2 IICAS0 0001 000B 3 IICAS0 0010 010B 4 IICAS0 0010 000B 5 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart does not match address extension code ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 5 6 2 1 4 1 IICAS0 0001 110B 2 IICAS0 0001 00B 3 IICAS0 0010 010B 4 IICAS0 0010 110B 5 IICAS0 0010 00B 6 IICAS0 ...

Page 482: ...o D0 ACK 3 4 2 1 1 IICAS0 0001 110B 2 IICAS0 0001 000B 3 IICAS0 00000110B 4 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart does not match address not extension code ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 2 1 1 IICAS0 0001 110B 2 IICAS0 0001 00B 3 IICAS0 00000110B 4 IICAS0 00000001B Remark Always ge...

Page 483: ...n WTIM0 0 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 1 IICAS0 0010 010B 2 IICAS0 0010 000B 3 IICAS0 0010 000B 4 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 5 2 1 1 IICAS0 0010 010B 2 IICAS0 0010 110B 3 IICAS0 0010 100B 4 IICAS0 0010 00B 5 IICAS0 00000001B Remark Always generat...

Page 484: ... 010B 2 IICAS0 0010 000B 3 IICAS0 0001 110B 4 IICAS0 0001 000B 5 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart matches SVA0 ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 6 2 1 5 1 IICAS0 0010 010B 2 IICAS0 0010 110B 3 IICAS0 0010 00B 4 IICAS0 0001 110B 5 IICAS0 0001 00B 6 IICAS0 00000001B Remark Always g...

Page 485: ...S0 0010 000B 3 IICAS0 0010 010B 4 IICAS0 0010 000B 5 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart extension code reception ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 7 2 1 5 6 1 IICAS0 0010 010B 2 IICAS0 0010 110B 3 IICAS0 0010 00B 4 IICAS0 0010 010B 5 IICAS0 0010 110B 6 IICAS0 0010 00B 7 IICAS0 0000...

Page 486: ... 2 1 1 IICAS0 00100010B 2 IICAS0 00100000B 3 IICAS0 00000110B 4 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 after restart does not match address not extension code ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 5 2 1 1 IICAS0 00100010B 2 IICAS0 00100110B 3 IICAS0 00100 00B 4 IICAS0 00000110B 5 IICAS0 00000001B Remark...

Page 487: ...ve after arbitration loss When the device is used as a master in a multi master system read the MSTS0 bit each time interrupt request signal INTIICA0 has occurred to check the arbitration result a When arbitration loss occurs during transmission of slave address data i When WTIM0 0 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 1 IICAS0 0101 110B 2 IICAS0 0001 000B 3 IICAS0 0001 000B 4...

Page 488: ... IICAS0 0001 00B 4 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care b When arbitration loss occurs during transmission of extension code i When WTIM0 0 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 1 IICAS0 0110 010B 2 IICAS0 0010 000B 3 IICAS0 0010 000B 4 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ...

Page 489: ...on t care 6 Operation when arbitration loss occurs no communication after arbitration loss When the device is used as a master in a multi master system read the MSTS0 bit each time interrupt request signal INTIICA0 has occurred to check the arbitration result a When arbitration loss occurs during transmission of slave address data when WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 2 1...

Page 490: ...K ACK SP 2 1 1 IICAS0 0110 010B Sets LREL0 1 by software 2 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care c When arbitration loss occurs during transmission of data i When WTIM0 0 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 2 1 1 IICAS0 10001110B 2 IICAS0 01000000B 3 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 ...

Page 491: ...AS0 00000001B Remark Always generated Generated only when SPIE0 1 d When loss occurs due to restart condition during data transfer i Not extension code Example unmatches with SVA0 ST AD6 to AD0 R W ACK D7 to Dn AD6 to AD0 ACK SP ST R W D7 to D0 ACK 3 2 1 1 IICAS0 1000 110B 2 IICAS0 01000110B 3 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care n 6 to 0 ...

Page 492: ...IICAS0 1000 110B 2 IICAS0 01100010B Sets LREL0 1 by software 3 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care n 6 to 0 e When loss occurs due to stop condition during data transfer ST AD6 to AD0 R W ACK D7 to Dn SP 2 1 1 IICAS0 10000110B 2 IICAS0 01000001B Remark Always generated Generated only when SPIE0 1 Don t care n 6 to 0 ...

Page 493: ...1 3 4 5 2 1 1 IICAS0 1000 110B 2 IICAS0 1000 000B Sets WTIM0 to 1 3 IICAS0 1000 100B Clears WTIM0 to 0 4 IICAS0 01000000B 5 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK SP ACK D7 to D0 ACK STT0 1 3 4 2 1 1 IICAS0 1000 110B 2 IICAS0 1000 100B Sets STT0 to 1 3 IICAS0 01000100B 4 IICAS0 00000001B Remark Alw...

Page 494: ...CK D7 to D0 ACK SP STT0 1 3 4 2 1 1 IICAS0 1000 110B 2 IICAS0 1000 000B Sets WTIM0 to 1 3 IICAS0 1000 00B Sets STT0 to 1 4 IICAS0 01000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 ACK SP STT0 1 2 3 1 1 IICAS0 1000 110B 2 IICAS0 1000 00B Sets STT0 to 1 3 IICAS0 01000001B Remark Always generated Generated only when SPIE0 1 Don t c...

Page 495: ...3 4 5 2 1 1 IICAS0 1000 110B 2 IICAS0 1000 000B Sets WTIM0 to 1 3 IICAS0 1000 100B Clears WTIM0 to 0 4 IICAS0 01000100B 5 IICAS0 00000001B Remark Always generated Generated only when SPIE0 1 Don t care ii When WTIM0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK SP ACK D7 to D0 ACK SPT0 1 3 4 2 1 1 IICAS0 1000 110B 2 IICAS0 1000 100B Sets SPT0 to 1 3 IICAS0 01000100B 4 IICAS0 00000001B Remark Alway...

Page 496: ... TRC0 bit bit 3 of the IICA status register 0 IICAS0 which specifies the data transfer direction and then starts serial communication with the slave device Figures 16 32 and 16 33 show timing charts of the data communication The IICA shift register IICA s shift operation is synchronized with the falling edge of the serial clock SCLA0 The transmit data is transferred to the SO latch and is output M...

Page 497: ... INTIICA0 TRC0 IICA ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIICA0 TRC0 SCLA0 SDAA0 1 2 3 4 5 6 7 8 9 4 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 W ACK D4 D5 D6 D7 Note 2 Processing by master device Transfer lines Processing by slave device IICA address IICA data Note 1 IICA FFH Note 2 Transmit Start condition Receive Notes 1 Write data to IICA not setting WREL0 in order to cancel a wait state...

Page 498: ...0 TRC0 IICA ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIICA0 TRC0 SCLA0 SDAA0 1 9 8 2 3 4 5 6 7 8 9 3 2 1 D7 D0 D6 D5 D4 D3 D2 D1 D0 D5 D6 D7 ACK ACK Processing by master device Transfer lines Processing by slave device IICA data Note 1 IICA FFH Note 2 IICA FFH Note 2 IICA data Note 1 Transmit Receive Note 2 Note 2 Notes 1 Write data to IICA not setting WREL0 in order to cancel a wait st...

Page 499: ...SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIICA0 TRC0 SCLA0 SDAA0 1 2 3 4 5 6 7 8 9 2 1 D7 D6 D5 D4 D3 D2 D1 D0 AD5 AD6 ACK Processing by master device Transfer lines Processing by slave device IICA data Note 1 IICA address IICA FFH Note 2 IICA FFH Note 2 Stop condition Start condition Transmit Note 2 Note 2 When SPIE0 1 Receive When SPIE0 1 Notes 1 Write data to IICA not setting WREL0 in order to ...

Page 500: ...EL0 INTIICA0 TRC0 IICA ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIICA0 TRC0 SCLA0 SDAA0 1 2 3 4 5 6 7 8 9 4 5 6 3 2 1 AD6 AD5 AD4 AD3 AD2 AD1 AD0 D4 D3 D2 D5 D6 D7 ACK R Processing by master device Transfer lines Processing by slave device IICA address IICA FFH Note 1 Note 1 IICA data Note 2 Transmit Transmit Receive Receive Notes 1 To cancel master wait write FFH to IICA or set WREL0 2...

Page 501: ...L0 INTIICA0 TRC0 IICA ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0 STT0 SPT0 WREL0 INTIICA0 TRC0 SCLA0 SDAA0 1 8 9 2 3 4 5 6 7 8 9 3 2 1 D7 D0 ACK D6 D5 D4 D3 D2 D1 D0 ACK D5 D6 D7 Processing by master device Transfer lines Processing by slave device Note 1 Note 1 Receive Transmit IICA data Note 2 IICA data Note 2 IICA FFH Note 1 IICA FFH Note 1 Notes 1 To cancel master wait write FFH to IICA or set WREL0 2 ...

Page 502: ... INTIICA0 TRC0 SCLA0 SDAA0 1 2 3 4 5 6 7 8 9 1 D7 D6 D5 D4 D3 D2 D1 D0 AD6 NACK Processing by master device Transfer lines Processing by slave device IICA address IICA FFH Note 1 IICA FFH Note 1 Note 1 Note 3 Notes 1 3 IICA data Note 2 Stop condition Start condition When SPIE0 1 When SPIE0 1 Receive Receive Transmit Notes 1 To cancel wait write FFH to IICA or set WREL0 2 Write data to IICA not set...

Page 503: ... 16 bits 32 bits 16 bit remainder division 17 2 Configuration of Multiplier Divider The multiplier divider includes the following hardware Table 17 1 Configuration of Multiplier Divider Item Configuration Registers Remainder data register 0 SDR0 Multiplication division data registers A0 MDA0H MDA0L Multiplication division data registers B0 MDB0 Control register Multiplier divider control register ...

Page 504: ...RS Start Clear 17 bit adder Controller Multiplication division data register B0 MDB0 MDB0H MDB0L Remainder data register 0 SDR0 SDR0H SDR0L 6 bit counter DMUSEL0 Multiplier divider control register 0 DMUC0 Controller Multiplication division data register A0 MDA0H MDA0HH MDA0HL MDA0L MDA0LH MDA0LL Controller DMUE MDA000 INTDMU ...

Page 505: ...2 bit register that sets a 16 bit multiplier A in the multiplication mode and a 32 bit dividend in the division mode and stores the 32 bit result of the operation higher 16 bits MDA0H lower 16 bits MDA0L Figure 17 3 Format of Multiplication Division Data Register A0 MDA0H MDA0L Address FF62H FF63H FF64H FF65H After reset 0000H 0000H R W Symbol FF65H MDA0HH FF64H MDA0HL MDA0H MDA 031 MDA 030 MDA 02...

Page 506: ...clock is input when bit 7 DMUE of multiplier divider control register 0 DMUC0 is set to 1 MDA0H and MDA0L can be set by an 8 bit or 16 bit memory manipulation instruction Reset signal generation clears MDA0H and MDA0L to 0000H 3 Multiplication division data register B0 MDB0 MDB0 is a register that stores a 16 bit multiplier B in the multiplication mode and a 16 bit divisor in the division mode MDB...

Page 507: ...6 7 5 Note When DMUE is set to 1 the operation is started DMUE is automatically cleared to 0 after the operation is complete Cautions 1 If DMUE is cleared to 0 during operation processing when DMUE is 1 the operation result is not guaranteed If the operation is completed while the clearing instruction is being executed the operation result is guaranteed provided that the interrupt flag is set 2 Do...

Page 508: ...n 16 peripheral hardware clocks fPRS have been issued after the start of the operation intermediate data is stored in the MDA0L and MDA0H registers during operation and therefore the read values of these registers are not guaranteed End of operation 4 The operation result data is stored in the MDA0L and MDA0H registers 5 DMUE is cleared to 0 end of operation 6 After the operation an interrupt requ...

Page 509: ...6 7 8 9 A B C D E F 10 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 006D 0000 00DA XXXX 00DA XXXX XXXX XXXX 0049 8036 0024 C01B 005B E00D 0077 7006 003B B803 0067 5C01 007D 2E00 003E 9700 001F 4B80 000F A5C0 0007 D2E0 0003 E970 0001 F4B8 0000 FA5C 0000 7D2E 0093 XXXX Internal clock DMUE DMUSEL0 Counter INTDMU ...

Page 510: ...e clocks fPRS have been issued after the start of the operation intermediate data is stored in the MDA0L and MDA0H registers and remainder data register 0 SDR0 during operation and therefore the read values of these registers are not guaranteed End of operation 4 The result data is stored in the MDA0L MDA0H and SDR0 registers 5 DMUE is cleared to 0 end of operation 6 After the operation an interru...

Page 511: ... 7 8 19 1A 1B 1C 1D 1E 1F 20 0 0 0000 0001 0003 0006 000D 0003 0007 000E 0004 000B 0016 0014 0010 0008 0011 000B 0016 B974 4B0C DCBA 2586 XXXX XXXX XXXX 72E8 9618 E5D1 2C30 CBA2 5860 9744 B0C1 2E89 6182 5D12 C304 BA25 8609 0C12 64D8 1824 C9B0 3049 9361 6093 26C3 C126 4D87 824C 9B0E 0499 361D 0932 6C3A 0018 XXXX Internal clock DMUE DMUSEL0 Counter INTDMU 0 ...

Page 512: ... having the same priority are simultaneously generated then they are processed according to the priority of vectored interrupt servicing For the priority order see Table 18 1 A standby release signal is generated and STOP and HALT modes are released External interrupt requests and internal interrupt requests are provided as maskable interrupts 2 Software interrupt This is a vectored interrupt gene...

Page 513: ...h between TM00 and CR000 when compare register is specified TI010 pin valid edge detection when capture register is specified 0020H 15 INTTM010 Match between TM00 and CR010 when compare register is specified TI000 pin valid edge detection when capture register is specified 0022H 16 INTAD End of A D conversion 0024H 17 INTIICA0 End of IICA communication 0026H 18 INTRTCI Real time counter interval s...

Page 514: ... detection 0032H Internal A 24 INTDMU End of multiply divide operation 0034H 25 INTP8 0038H Maskable External B 26 INTP9 Pin input edge detection 003AH Software D BRK BRK instruction execution 003EH RESET Reset input POC Power on clear LVI Low voltage detection Note 3 Reset WDT WDT overflow 0000H Notes 1 Basic configuration types A to D correspond to A to D in Figure 18 1 2 The default priority de...

Page 515: ...rator Standby release signal B External maskable interrupt INTPn Internal bus Interrupt request IF MK IE PR ISP Priority controller Vector table address generator Standby release signal External interrupt edge enable register EGP0 EGP1 EGN0 EGN1 Edge detector Remark n 0 1 4 to 7 78K0 KB2 A n 0 to 9 78K0 KC2 A IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interr...

Page 516: ... Priority controller Vector table address generator Standby release signal Key interrupt detector 1 when KRMn 1 Remark n 0 to 5 78K0 KC2 A D Software interrupt Internal bus Interrupt request Priority controller Vector table address generator IF Interrupt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority specification flag KRM Key return mode regi...

Page 517: ...terrupt mask flags and priority specification flags corresponding to interrupt request sources Table 18 2 Flags Corresponding to Interrupt Request Sources 1 2 Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag 78K0 KB2 A 78K0 KC2 A Interrupt Source Register Register Register INTLVI LVIIF IF0L LVIMK MK0L LVIPR PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2 PMK2 PPR2 I...

Page 518: ...F1L ADMK MK1L ADPR PR1L INTIICA0 IICAIF0 IICAMK0 IICAPR0 INTRTCI RTCIIF RTCIMK RTCIPR INTTM51 Note TMIF51 TMMK51 TMPR51 INTKR KRIF KRMK KRPR INTRTC RTCIF RTCMK RTCPR INTP6 PIF6 PMK6 PPR6 INTP7 PIF7 PMK7 PPR7 INTDMU DMUIF DMUMK DMUPR INTP8 PIF8 IF1H PMK8 PPR8 INTP9 PIF9 PMK9 MK1H PPR9 PR1H Note When 8 bit timer event counter 51 is used in the carrier generator mode an interrupt is generated upon th...

Page 519: ...ions 1 When operating a timer serial interface or A D converter after standby release operate it once after clearing the interrupt request flag An interrupt request flag may be set by noise 2 When manipulating a flag of the interrupt request flag register use a 1 bit memory manipulation instruction CLR1 When describing in C language use a bit manipulation instruction such as IF0L 0 0 or _asm clr1 ...

Page 520: ...bol 7 6 5 4 3 2 1 0 IF0H TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 CSIIF10 STIF6 SRIF6 Address FFE2H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF1L PIF7 PIF6 0 0 TMIF51 0 IICAIF0 ADIF Address FFE3H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF1H 0 0 0 0 0 0 0 DMUIF XXIFX Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated interrupt request status Caution ...

Page 521: ...reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0H TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 CSIIF10 STIF6 SRIF6 Address FFE2H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF1L PIF7 PIF6 RTCIF KRIF TMIF51 RTCIIF IICAIF0 ADIF Address FFE3H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF1H 0 0 0 0 PIF9 PIF8 0 DMUIF XXIFX Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generate...

Page 522: ...s to FFH Figure 18 3 Format of Interrupt Mask Flag Registers MK0L MK0H MK1L MK1H 1 2 1 78K0 KB2 A Address FFE4H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0L SREMK6 PMK5 PMK4 1 1 PMK1 PMK0 LVIMK Address FFE5H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1 CSIMK10 STMK6 SRMK6 Address FFE6H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK1L PMK7 PMK6 1 1 TMMK51 1...

Page 523: ...ress FFE5H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0H TMMK010 TMMK000 TMMK50 TMMKH0 TMMKH1 CSIMK10 STMK6 SRMK6 Address FFE6H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK1L PMK7 PMK6 RTCMK KRMK TMMK51 RTCIMK IICAMK0 ADMK Address FFE7H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK1H 1 1 1 1 PMK9 PMK8 1 DMUMK XXMKX Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing ...

Page 524: ... these registers to FFH Figure 18 4 Format of Priority Specification Flag Registers PR0L PR0H PR1L PR1H 1 2 1 78K0 KB2 A Address FFE8H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0L SREPR6 PPR5 PPR4 1 1 PPR1 PPR0 LVIPR Address FFE9H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR0H TMPR010 TMPR000 TMPR50 TMPRH0 TMPRH1 CSIPR10 STPR6 SRPR6 Address FFEAH After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR1L...

Page 525: ...4 3 2 1 0 PR1L PPR7 PPR6 RTCPR KRPR TMPR51 RTCIPR IICAPR0 ADPR Address FFEBH After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR1H 1 1 1 1 PPR9 PPR8 1 DMUPR XXPRX Priority level selection 0 High priority level 1 Low priority level Caution Be sure to set bits 1 and 4 to 7 of PR1H to 1 4 External interrupt rising edge enable register EGP0 EGP1 external interrupt falling edge enable register EGN0 EGN1 Thes...

Page 526: ...Symbol 7 6 5 4 3 2 1 0 EGP0 EGP7 EGP6 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0 Address FF49H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGN0 EGN7 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 Address FF4AH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGP1 0 0 0 0 0 0 EGP9 EGP8 Address FF4BH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 EGN1 0 0 0 0 0 0 EGN9 EGN8 EGPn EGNn INTPn pin valid edge selection 0 0 Edge detection di...

Page 527: ...NTP0 EGP1 EGN1 P35 INTP1 EGP2 EGN2 P34 Note INTP2 Note EGP3 EGN3 P33 Note INTP3 Note EGP4 EGN4 P32 INTP4 EGP5 EGN5 P31 INTP5 EGP6 EGN6 P13 INTP6 EGP7 EGN7 P12 INTP7 EGP8 EGN8 P02 Note INTP8 Note EGP9 EGN9 P42 Note INTP9 Note Note 78K0 KC2 A only Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected when the external interrupt function is switched to the port f...

Page 528: ...o a stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP flag The PSW contents are also saved into the stack with the PUSH PSW instruction They are restored from the stack with the RETI RETB and POP PSW instructions Reset signal generation sets PSW to 02H Figure 1...

Page 529: ... PR 0 7 clocks 32 clocks When PR 1 8 clocks 33 clocks Note If an interrupt request is generated just before a divide instruction the wait time becomes longer Remark 1 clock 1 fCPU fCPU CPU clock If two or more maskable interrupt requests are generated simultaneously the request with a higher priority level specified in the priority specification flag is acknowledged first If two or more interrupts...

Page 530: ...eld pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Interrupt request held pending Vectored interrupt servicing Any high priority interrupt request among those simultaneously generated Any high priority interrupt request among those simultaneously generated with PR 0 IF Interrupt request flag MK Interrupt mask flag PR Priority specification flag...

Page 531: ...servicing program CPU processing IF PR 1 IF PR 0 6 clocks 25 clocks Remark 1 clock 1 fCPU fCPU CPU clock 18 4 2 Software interrupt request acknowledgment A software interrupt acknowledge is acknowledged by BRK instruction execution Software interrupts cannot be disabled If a software interrupt request is acknowledged the contents are saved into the stacks in the order of the program status word PS...

Page 532: ...ntly being serviced is generated during interrupt servicing it is not acknowledged for multiple interrupt servicing Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending When servicing of the current interrupt ends the pending interrupt request is acknowledged following execution of at least one main pr...

Page 533: ...dged the EI instruction must always be issued to enable interrupt request acknowledgment Example 2 Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing INTxx PR 0 INTyy PR 1 EI RETI IE 0 IE 0 EI 1 instruction execution RETI IE 1 IE 1 Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its prio...

Page 534: ...instruction execution RETI RETI INTxx PR 0 INTyy PR 0 IE 0 IE 0 IE 1 IE 1 Interrupts are not enabled during servicing of interrupt INTxx EI instruction is not issued therefore interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one main processing instruction PR 0 Hig...

Page 535: ...1L IF1H MK0L MK0H MK1L MK1H PR0L PR0H PR1L and PR1H registers Caution The BRK instruction is not one of the above listed interrupt request hold instructions However the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared Therefore even if a maskable interrupt request is generated during execution of the BRK instruction the interrupt request is not acknowl...

Page 536: ...terrupt 6 ch 19 1 Functions of Key Interrupt A key interrupt INTKR can be generated by setting the key return mode register KRM and inputting a falling edge to the key interrupt input pins KRn Table 19 1 Assignment of Key Interrupt Detection Pins Flag Description KRMn Controls KRn signal in 1 bit units Remark n 0 5 ...

Page 537: ...rrupt The key interrupt includes the following hardware Table 19 2 Configuration of Key Interrupt Item Configuration Control register Key return mode register KRM Figure 19 1 Block Diagram of Key Interrupt INTKR 0 0 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 KR5 KR4 KR3 KR2 KR1 KR0 Key return mode register KRM ...

Page 538: ...bol 7 6 5 4 3 2 1 0 KRM 0 0 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 KRMn Key interrupt mode control 0 Does not detect key interrupt signal 1 Detects key interrupt signal Cautions 1 If any of the KRMn bits used is set to 1 set bit n PU7n of the corresponding pull up resistor register 7 PU7 to 1 2 If KRM is changed the interrupt request flag may be set Therefore disable interrupts and then change the KRM regi...

Page 539: ...ucing the CPU operating current Because this mode can be cleared by an interrupt request it enables intermittent operations to be carried out However because a wait time is required to secure the oscillation stabilization time after the STOP mode is released when the X1 clock is selected select the HALT mode if it is necessary to start processing immediately upon interrupt request generation In ei...

Page 540: ...CK GENERATOR 1 Oscillation stabilization time counter status register OSTC This is the register that indicates the count status of the X1 clock oscillation stabilization time counter When X1 clock oscillation starts with the internal high speed oscillation clock or subsystem clock used as the CPU clock the X1 clock oscillation stabilization time can be checked OSTC can be read by a 1 bit or 8 bit ...

Page 541: ...lation stabilization time as follows Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note therefore that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is released 3 The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts a below STOP mode release X1 pin vol...

Page 542: ... set by OSTS If the STOP mode is entered and then released while the internal high speed oscillation clock is being used as the CPU clock set the oscillation stabilization time as follows Desired OSTC oscillation stabilization time Oscillation stabilization time set by OSTS Note therefore that only the status up to the oscillation stabilization time set by OSTS is set to OSTC after STOP mode is re...

Page 543: ...on continues cannot be stopped Subsystem clock fSUB Status before HALT mode was set is retained Internal low speed oscillation clock fRL Status before HALT mode was set is retained CPU Flash memory Operation stopped RAM Port latch Status before HALT mode was set is retained 16 bit timer event counter 00 50 8 bit timer event counter 51 H0 8 bit timer H1 Real time counter RTC Operable Watchdog timer...

Page 544: ... stopped 50 Note 8 bit timer event counter 51 Note H0 8 bit timer H1 Real time counter RTC Operable Watchdog timer Operable Clock supply to watchdog timer stops when internal low speed oscillator can be stopped by software is set by option byte Clock output Operable A D converter Not operable Operational amplifier Disables operation UART6 CSI10 Note Serial interface IICA Note Multiplier divider Po...

Page 545: ...20 3 HALT Mode Release by Interrupt Request Generation HALT instruction WaitNote 1 Normal operation HALT mode Normal operation Oscillation High speed system clock internal high speed oscillation clock or subsystem clockNote 2 Status of CPU Standby release signal Interrupt request Notes 1 The wait time is as follows When vectored interrupt servicing is carried out 11 or 12 clocks When vectored inte...

Page 546: ...are Reset processing 11 to 45 s μ 2 When internal high speed oscillation clock is used as CPU clock HALT instruction Reset signal Internal high speed oscillation clock Normal operation internal high speed oscillation clock HALT mode Reset period Normal operation internal high speed oscillation clock Oscillates Oscillation stopped Oscillates Status of CPU Wait for oscillation accuracy stabilization...

Page 547: ...he STOP mode is set by executing the STOP instruction and it can be set only when the CPU clock before the setting was the main system clock Caution Because the interrupt request signal is used to clear the standby mode if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset the standby mode is immediately cleared if set Thus the STOP mode is reset to ...

Page 548: ...g 8 bit timer event counter 50 operation 8 bit timer H1 Operable only when fRL fRL 2 7 fRL 2 9 is selected as the count clock Real time counter RTC Operable only when subsystem clock is selected as the count clock Watchdog timer Operable Clock supply to watchdog timer stops when internal low speed oscillator can be stopped by software is set by option byte Clock output Operable only when subsystem...

Page 549: ...struction using the following procedure 1 Set RSTOP to 0 starting oscillation of the internal high speed oscillator 2 Set MCM0 to 0 switching the CPU from X1 oscillation to internal high speed oscillation 3 Check that MCS is 0 checking the CPU clock 4 Check that RSTS is 1 checking internal high speed oscillation operation 5 Execute the STOP instruction Before changing the CPU clock from the intern...

Page 550: ...on stabilization time set by OSTS Clock switched by software Clock switched by software High speed system clock High speed system clock WaitNote2 WaitNote2 Supply of the CPU clock is stopped 4 06 to 16 12 s Note1 High speed system clock μ Supply of the CPU clock is stopped 160 external clocks Note1 Internal high speed oscillation clock Notes 1 When AMPH 1 2 The wait time is as follows When vectore...

Page 551: ...OP instruction Standby release signal Status of CPU High speed system clock external clock input Oscillates Normal operation high speed system clock STOP mode Oscillation stopped Oscillates Normal operation high speed system clock WaitNote Supply of the CPU clock is stopped 160 external clocks When AMPH 0 Interrupt request STOP instruction Standby release signal Status of CPU High speed system clo...

Page 552: ...al high speed oscillation clock Supply of the CPU clock is stopped μ Oscillates When AMPH 0 WaitNote Wait for oscillation accuracy stabilization 86 to 361 s Oscillates Normal operation internal high speed oscillation clock STOP mode Oscillation stopped Oscillates Normal operation internal high speed oscillation clock Internal high speed oscillation clock Status of CPU Standby release signal STOP i...

Page 553: ...ation is specified by software Oscillation stopped Reset processing 11 to 45 s μ 2 When internal high speed oscillation clock is used as CPU clock STOP instruction Reset signal Internal high speed oscillation clock Normal operation internal high speed oscillation clock STOP mode Reset period Normal operation internal high speed oscillation clock Oscillates Oscillation stopped Status of CPU Oscilla...

Page 554: ...elease When a low level is input to the RESET pin the device is reset It is released from the reset status when a high level is input to the RESET pin and program execution is started with the internal high speed oscillation clock after reset processing A reset by the watchdog timer is automatically released and program execution starts using the internal high speed oscillation clock see Figures 2...

Page 555: ...tchdog timer reset signal RESET Power on clear circuit reset signal Low voltage detector reset signal Reset signal Reset signal to LVIM LVIS register Clear Set Clear Set RESF register read signal Caution An LVI circuit internal reset does not reset the LVI circuit Remarks 1 LVIM Low voltage detection register 2 LVIS Low voltage detection level selection register ...

Page 556: ... Reset processing 11 to 45 s μ μ Wait for oscillation accuracy stabilization 86 to 361 s μ Figure 21 3 Timing of Reset Due to Watchdog Timer Overflow Normal operation Reset period oscillation stop CPU clock Watchdog timer overflow Internal reset signal Hi Z Port pin High speed system clock when X1 oscillation is selected Internal high speed oscillation clock Starting X1 oscillation is specified by...

Page 557: ...peed system clock when X1 oscillation is selected Internal high speed oscillation clock Hi Z Port pin Starting X1 oscillation is specified by software Normal operation internal high speed oscillation clock Reset processing 11 to 45 s Delay 5 s TYP μ μ Wait for oscillation accuracy stabilization 86 to 361 s μ Remarks 1 For the reset timing of the power on clear circuit and low voltage detector see ...

Page 558: ...nal low speed oscillation clock fRL CPU Flash memory RAM Port latch 16 bit timer event counter 00 50 8 bit timer event counter 51 H0 8 bit timer H1 Real time counter RTC Watchdog timer Clock output A D converter UART6 CSI10 Serial interface IICA Multiplier divider Operation stopped Power on clear function Operable Low voltage detection function External interrupt Operation stopped Remarks 1 fRH In...

Page 559: ...rnal memory size switching register IMS CFH Note 3 Notes 1 During reset signal generation or oscillation stabilization time wait only the PC contents among the hardware statuses become undefined All other hardware statuses remain unchanged after reset 2 When a reset is executed in the standby mode the pre reset status is held even after reset 3 The initial values of the internal memory size switch...

Page 560: ...er event counters 50 51 Mode control registers 50 51 TMC50 TMC51 00H Compare registers 00 10 01 11 CMP00 CMP10 CMP01 CMP11 00H Mode registers TMHMD0 TMHMD1 00H 8 bit timers H0 H1 Carrier control register 1 TMCYC1 Note 2 00H Sub count register RSUBC 0000H Second count register SEC 00H Minute count register MIN 00H Hour count register HOUR 12H Week count register WEEK 00H Day count register DAY 01H ...

Page 561: ...ol register 6 ASICL6 16H Serial interface UART6 Input switch control register ISC 00H Transmit buffer register 10 SOTB10 00H Serial I O shift register 10 SIO10 00H Serial operation mode register 10 CSIM10 00H Serial interface CSI10 Serial clock selection register 10 CSIC10 00H Shift register IICA 00H Status register 0 IICAS0 00H Flag register 0 IICAF0 00H Control register 0 IICACTL0 00H Control re...

Page 562: ...1L 1H PR0L PR0H PR1L PR1H FFH External interrupt rising edge enable register EGP0 EGP1 00H Interrupt External interrupt falling edge enable register EGN0 EGN1 00H Notes 1 During reset signal generation or oscillation stabilization time wait only the PC contents among the hardware statuses become undefined All other hardware statuses remain unchanged after reset 2 These values vary depending on the...

Page 563: ... 3 2 1 0 RESF 0 0 0 WDTRF 0 0 0 LVIRF WDTRF Internal reset request by watchdog timer WDT 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated LVIRF Internal reset request by low voltage detector LVI 0 Internal reset request is not generated or RESF is cleared 1 Internal reset request is generated Note The value after reset varies depending on the reset...

Page 564: ...DD exceeds 2 7 V 0 2 V Compares supply voltage VDD and detection voltage VPOC 1 59 V 0 15 V generates internal reset signal when VDD VPOC Caution If an internal reset signal is generated in the POC circuit the reset control flag register RESF is cleared to 00H Remark 78K0 Kx2 A microcontrollers incorporate multiple hardware functions that generate an internal reset signal A flag that indicates the...

Page 565: ... 59 V 0 15 V the reset status is released The supply voltage VDD and detection voltage VPOC 1 59 V 0 15 V are compared When VDD VPOC the internal reset signal is generated It is released when VDD VPOC 2 In 2 7 V 1 59 V POC mode option byte POCMODE 1 An internal reset signal is generated on power application When the supply voltage VDD exceeds the detection voltage VDDPOC 2 7 V 0 2 V the reset stat...

Page 566: ...ing 11 to 45 s μ Reset processing 11 to 45 s μ μ VPOC 1 59 V TYP VLVI Notes 1 The guaranteed operation range is 1 8 V VDD 5 5 V To set the voltage range below the guaranteed operation range to the reset state when the supply voltage falls use the reset function of the low voltage detector or input a low level to the RESET pin 2 If the voltage rises to 1 8 V at a rate slower than 0 5 V ms MIN on po...

Page 567: ...61 s μ Wait for oscillation accuracy stabilization 86 to 361 s μ Wait for oscillation accuracy stabilization 86 to 361 s μ Notes 1 The guaranteed operation range is 1 8 V VDD 5 5 V To set the voltage range below the guaranteed operation range to the reset state when the supply voltage falls use the reset function of the low voltage detector or input a low level to the RESET pin 2 The CPU clock can...

Page 568: ... that uses a timer and then initialize the ports Figure 22 3 Example of Software Processing After Reset Release 1 2 If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage Check the reset sourceNote 2 Initialize the port Note 1 Reset Initialization processing 1 50 ms has passed TMIFH1 1 Initialization processing 2 Setting 8 bit timer H1 to measure 50 ms Setting of divis...

Page 569: ...3 Example of Software Processing After Reset Release 2 2 Checking reset source Yes No Check reset source Power on clear external reset generated Reset processing by watchdog timer Reset processing by low voltage detector No WDTRF of RESF register 1 LVIRF of RESF register 1 Yes ...

Page 570: ...ection of Input Voltage from External Input Pin EXLVI LVISEL 1 Selects reset LVIMD 1 Selects interrupt LVIMD 0 Selects reset LVIMD 1 Selects interrupt LVIMD 0 Generates an internal reset signal when VDD VLVI and releases the reset signal when VDD VLVI Generates an internal interrupt signal when VDD drops lower than VLVI VDD VLVI or when VDD becomes VLVI or higher VDD VLVI Generates an internal res...

Page 571: ...Internal reset signal 4 LVISEL EXLVI P120 INTP0 LVIMD VDD Low voltage detection level selector Selector Selector 23 3 Registers Controlling Low Voltage Detector The low voltage detector is controlled by the following registers Low voltage detection register LVIM Low voltage detection level selection register LVIS Port mode register 12 PM12 1 Low voltage detection register LVIM This register sets l...

Page 572: ...gnal when EXLVI VEXLVI LVIF Low voltage detection flag 0 LVISEL 0 Supply voltage VDD detection voltage VLVI or when operation is disabled LVISEL 1 Input voltage from external input pin EXLVI detection voltage VEXLVI or when operation is disabled 1 LVISEL 0 Supply voltage VDD detection voltage VLVI LVISEL 1 Input voltage from external input pin EXLVI detection voltage VEXLVI Notes 1 This bit is cle...

Page 573: ...1 VLVI1 4 09 V 0 1 V 0 0 1 0 VLVI2 3 93 V 0 1 V 0 0 1 1 VLVI3 3 78 V 0 1 V 0 1 0 0 VLVI4 3 62 V 0 1 V 0 1 0 1 VLVI5 3 47 V 0 1 V 0 1 1 0 VLVI6 3 32 V 0 1 V 0 1 1 1 VLVI7 3 16 V 0 1 V 1 0 0 0 VLVI8 3 01 V 0 1 V 1 0 0 1 VLVI9 2 85 V 0 1 V 1 0 1 0 VLVI10 2 70 V 0 1 V 1 0 1 1 VLVI11 2 55 V 0 1 V 1 1 0 0 VLVI12 2 39 V 0 1 V 1 1 0 1 VLVI13 2 24 V 0 1 V 1 1 1 0 VLVI14 2 08 V 0 1 V 1 1 1 1 VLVI15 1 93 V 0...

Page 574: ...nerates an internal reset signal when VDD VLVI and releases internal reset when VDD VLVI If LVISEL 1 compares the input voltage from external input pin EXLVI and detection voltage VEXLVI 1 21 V TYP generates an internal reset signal when EXLVI VEXLVI and releases internal reset when EXLVI VEXLVI 2 Used as interrupt LVIMD 0 If LVISEL 0 compares the supply voltage VDD and detection voltage VLVI When...

Page 575: ...l it is checked that supply voltage VDD detection voltage VLVI by bit 0 LVIF of LVIM 7 Set bit 1 LVIMD of LVIM to 1 generates reset when the level is detected Figure 23 5 shows the timing of the internal reset signal generated by the low voltage detector The numbers in this timing chart correspond to 1 to 7 above Cautions 1 1 must always be executed When LVIMK 0 an interrupt may occur immediately ...

Page 576: ...oftware Not cleared Not cleared Not cleared Not cleared Cleared by software 4 7 Clear Clear Clear 5 Wait time LVION flag set by software LVIMD flag set by software HNote 1 L LVISEL flag set by software 6 2 VLVI VPOC 1 59 V TYP Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The LVIF flag may be set 1 3 LVIRF is bit 0 of the reset control flag register RESF For details of RESF see C...

Page 577: ...y software Not cleared Not cleared Not cleared Not cleared Cleared by software 4 7 Clear Clear Clear 5 Wait time LVION flag set by software LVIMD flag set by software HNote 1 L LVISEL flag set by software 6 2 2 7 V TYP VPOC 1 59 V TYP Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The LVIF flag may be set 1 3 LVIRF is bit 0 of the reset control flag register RESF For details of RE...

Page 578: ...it 1 LVIMD of LVIM to 1 generates reset signal when the level is detected Figure 23 6 shows the timing of the internal reset signal generated by the low voltage detector The numbers in this timing chart correspond to 1 to 6 above Cautions 1 1 must always be executed When LVIMK 0 an interrupt may occur immediately after the processing in 3 2 If input voltage from external input pin EXLVI detection ...

Page 579: ...ared Not cleared Not cleared Not cleared Cleared by software 3 6 LVION flag set by software LVIMD flag set by software HNote 1 LVISEL flag set by software 5 2 Not cleared Not cleared 4 Wait time Not cleared Not cleared Not cleared Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The LVIF flag may be set 1 3 LVIRF is bit 0 of the reset control flag register RESF For details of RESF s...

Page 580: ...6 Use software to wait for an operation stabilization time 10 μs MIN 7 Confirm that supply voltage VDD detection voltage VLVI when detecting the falling edge of VDD or supply voltage VDD detection voltage VLVI when detecting the rising edge of VDD at bit 0 LVIF of LVIM 8 Clear the interrupt request flag of LVI LVIIF to 0 9 Release the interrupt mask flag of LVI LVIMK 10 Execute the EI instruction ...

Page 581: ...t time LVION flag set by software Note 2 Note 2 3 L LVISEL flag set by software 2 LVIMD flag set by software L 4 Note 2 Note 3 Note 3 VLVI VPOC 1 59 V TYP Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The interrupt request signal INTLVI is generated and the LVIF and LVIIF flags may be set 1 3 If LVION is cleared 0 in a state below the LVI detection voltage an INTLVI signal is gen...

Page 582: ...time LVION flag set by software Note 2 Note 2 3 L LVISEL flag set by software 2 LVIMD flag set by software L 4 2 7 V TYP Note 2 Note 3 Note 3 VLVI VPOC 1 59 V TYP Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The interrupt request signal INTLVI is generated and the LVIF and LVIIF flags may be set 1 3 If LVION is cleared 0 in a state below the LVI detection voltage an INTLVI signa...

Page 583: ...tion voltage VEXLVI 1 21 V TYP when detecting the falling edge of EXLVI or input voltage from external input pin EXLVI detection voltage VEXLVI 1 21 V TYP when detecting the rising edge of EXLVI at bit 0 LVIF of LVIM 7 Clear the interrupt request flag of LVI LVIIF to 0 8 Release the interrupt mask flag of LVI LVIMK 9 Execute the EI instruction when vector interrupts are used Figure 23 8 shows the ...

Page 584: ...lag set by software Note 2 Note 2 LVISEL flag set by software 2 LVIMD flag set by software L 3 Note 2 Note 3 Note 3 VEXLVI Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 The interrupt request signal INTLVI is generated and the LVIF and LVIIF flags may be set 1 3 If LVION is cleared 0 in a state below the LVI detection voltage an INTLVI signal is generated and LVIIF becomes 1 Remar...

Page 585: ...e ports see Figure 23 9 2 When used as interrupt a Confirm that supply voltage VDD detection voltage VLVI when detecting the falling edge of VDD or supply voltage VDD detection voltage VLVI when detecting the rising edge of VDD in the servicing routine of the LVI interrupt by using bit 0 LVIF of the low voltage detection register LVIM Clear bit 0 LVIIF of interrupt request flag register 0L IF0L to...

Page 586: ...d TMIFH1 1 Initialization processing 2 Setting 8 bit timer H1 to measure 50 ms Setting of division ratio of system clock such as setting of timer or A D converter Yes No Clearing WDT Detection voltage or higher LVIF 0 Yes Restarting timer H1 TMHE1 0 TMHE1 1 No The timer counter is cleared and the timer is started LVI reset fPRS Internal high speed oscillation clock 8 4 MHz MAX default Source fPRS ...

Page 587: ...9780EJ2V0UD 585 Figure 23 9 Example of Software Processing After Reset Release 2 2 Checking reset source Yes Reset generation by LVI No Reset generation other than by LVI Set LVI Set LVIM and LVIS registers Check reset source LVION of LVIM register 1 ...

Page 588: ...same as that of 0080H to 1080H because 0080H and 1080H are switched during the boot swap operation 2 0081H 1081H Selecting POC mode During 2 7 V 1 59 V POC mode operation POCMODE 1 The device is in the reset state upon power application and until the supply voltage reaches 2 7 V TYP It is released from the reset state when the voltage exceeds 2 7 V TYP After that POC is not detected at 2 7 V but i...

Page 589: ...a of the flash memory in case authentication of the on chip debug security ID fails Enabling on chip debug operation and not erasing data of the flash memory even in case authentication of the on chip debug security ID fails Caution Set 00H to 1084H because 0084H and 1084H are switched during the boot operation 24 2 Format of Option Byte The format of the option byte is shown below ...

Page 590: ...gister 1 Cannot be stopped not stopped even if 1 is written to LSRSTOP bit Note Also set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the boot swap operation Cautions 1 The combination of WDCS2 WDCS1 WDCS0 0 and WINDOW1 WINDOW0 0 is prohibited 2 Setting WINDOW1 WINDOW0 0 is prohibited when using the watchdog timer at 1 8 V VDD 2 7 V 3 The watchdog ...

Page 591: ... changed after the memory of the specified block is erased Caution Be sure to clear bits 7 to 1 to 0 Address 0082H 1082H 0083H 1083H Note 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Note Be sure to set 00H to 0082H and 0083H as these addresses are reserved areas Also set 00H to 1082H and 1083H because 0082H and 0083H are switched with 1082H and 1083H when the boot swap operation is used Address 0084H 1084H No...

Page 592: ...l access detection operation Window open period of watchdog timer 50 Overflow time of watchdog timer 210 fRL Internal low speed oscillator can be stopped by software DB 00H 1 59 V POC mode DB 00H Reserved area DB 00H Reserved area DB 00H On chip debug operation disabled Remark Referencing of the option byte is performed during reset processing For the reset processing timing see CHAPTER 21 RESET F...

Page 593: ...tion Be sure to set each product to the values shown in Table 25 1 after a reset release Figure 25 1 Format of Internal Memory Size Switching Register IMS Address FFF0H After reset CFH R W Symbol 7 6 5 4 3 2 1 0 IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 RAM2 RAM1 RAM0 Internal high speed RAM capacity selection 1 1 0 1024 bytes Other than above Setting prohibited ROM3 ROM2 ROM1 ROM0 Internal ROM cap...

Page 594: ...ntrollers are mounted on the target system Remark The FA series is a product of Naito Densei Machida Mfg Co Ltd 25 3 Programming Environment The environment required for writing a program to the flash memory of the 78K0 Kx2 A microcontrollers are illustrated below Figure 25 2 Environment for Writing Program to Flash Memory RS 232C USB microcontrollers FLMD0 VDD VSS RESET CSI10 UART6 Host machine D...

Page 595: ...CK Dedicated flash memory programmer microcontrollers PG FP5 START POWER PASS BUSY N G Caution Only the P60 SCLA0 SCK10 and P61 SDAA0 SI10 pins when used as the CSI10 pins SCK10 and SI10 can be used for communicating with the dedicated flash memory programmer The P31 INTP5 OCD1A SCK10 and P32 INTP4 OCD1B SI10 pins cannot be used for communicating with the dedicated flash memory programmer 2 UART6 ...

Page 596: ... used Remark Be sure to connect the pin The pin does not have to be connected if the signal is generated on the target board The pin does not have to be connected 25 5 Connection of Pins on Board To write the flash memory on board connectors that connect the dedicated flash memory programmer must be provided on the target system First provide a function that selects the normal operation mode or fl...

Page 597: ...collision If the dedicated flash memory programmer output is connected to a pin input of a serial interface connected to another device output signal collision takes place To avoid this collision either isolate the connection with the other device or make the other device go into an output high impedance state Figure 25 6 Signal Collision Input Pin of Serial Interface Input pin Signal collision De...

Page 598: ...ash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board signal collision takes place To prevent this collision isolate the connection with the reset signal generator If the reset signal is input from the user system while the flash memory programming mode is set the flash memory will not be correctly programmed Do not input any signal other ...

Page 599: ...s 1 Only the internal high speed oscillation clock fRH can be used when CSI10 is used 2 Only the X1 clock fX or external main system clock fEXCLK can be used when UART6 is used 3 Connect P31 INTP5 OCD1A and P121 X1 OCD0A as follows when writing the flash memory with a flash memory programmer P31 INTP5 OCD1A Connect to VSS via a resistor P121 X1 OCD0A Open or connect to VSS via a resistor 25 5 7 Po...

Page 600: ...ng mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer set the 78K0 Kx2 A microcontrollers in the flash memory programming mode To set the mode set the FLMD0 pin to VDD and clear the reset signal Change the mode by using a jumper when writing the flash memory on board Figure 25 10 Flash Memory Programming Mode VDD RESET 5 5 V 0 V VDD 0 V Flash memory pro...

Page 601: ...RT Ext FP5CK 115 200 bps Note 3 2 to 20 MHz Note 2 TxD6 RxD6 fEXCLK 3 3 wire serial I O CSI10 CSI Internal OSC 2 4 kHz to 2 5 MHz 1 0 SO10 SI10 SCK10 fRH 8 Notes 1 Selection items for Standard settings on GUI of the flash memory programmer 2 The possible setting range differs depending on the voltage For details refer to the chapter of electrical specifications 3 Because factors other than the bau...

Page 602: ...ts of a specified area of the flash memory with data transmitted from the programmer Chip Erase Erases the entire flash memory Erase Block Erase Erases a specified area in the flash memory Blank check Block Blank Check Checks if a specified block in the flash memory has been correctly erased Write Programming Writes data to a specified area in the flash memory Status Gets the current operating sta...

Page 603: ... block erase command for a specific block in the flash memory is prohibited during on board off board programming However blocks can be erased by means of self programming Disabling write Execution of the write and block erase commands for entire blocks in the flash memory is prohibited during on board off board programming However blocks can be written by means of self programming Disabling rewri...

Page 604: ...on of block erase Prohibition of writing Blocks can be erased Can be performed Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased Boot cluster 0 cannot be written Table 25 9 shows how to perform security settings in each programming mode Table 25 9 Setting Security in Each Programming Mode 1 On board off board programming Security Security Setting How to Disable Security Setti...

Page 605: ...STOP flag bit 0 of the internal oscillation mode register RCM Oscillation of the internal high speed oscillator cannot be stopped even if the STOP instruction is executed 3 Input a high level to the FLMD0 pin during self programming 4 Be sure to execute the DI instruction before starting self programming The self programming function checks the interrupt request flags IF0L IF0H IF1L and IF1H If an...

Page 606: ...ng FlashStart Normal completion No Setting operating environment FlashEnv CheckFLMD FlashBlockBlankCheck Yes FlashBlockErase FlashWordWrite FlashBlockVerify FlashEnd End of self programming Normal completion No Yes Normal completion Normal completion Error No Yes FlashBlockErase FlashWordWrite FlashBlockVerify Remark For details of the self programming library refer to 78K0 Microcontrollers Self P...

Page 607: ...994 0 EEPROM write library 1316 8 347 w 1320 9 2385 w 1309 0 347 w 1312 4 2385 w 2 When internal high speed oscillation clock is used and entry RAM is located in short direct addressing range Processing Time μs Normal Model of C Compiler Static Model of C Compiler Assembler Library Name Min Max Min Max Self programming start library 4 0 4 5 4 0 4 5 Initialize library 449 5 450 2 449 5 450 2 Mode c...

Page 608: ...rary 333 fCPU 647 136 w 333 fCPU 647 1647 w 272 fCPU 647 136 w 272 fCPU 647 1647 w Block verify library 179 fCPU 13284 136 fCPU 13284 Self programming end library 34 fCPU Option value 03H 180 fCPU 581 134 fCPU 581 Option value 04H 190 fCPU 574 144 fCPU 574 Get information library Option value 05H 350 fCPU 535 304 fCPU 535 Set information library 80 fCPU 43181 80 fCPU 572934 72 fCPU 43181 72 fCPU 5...

Page 609: ...y 333 fCPU 247 136 w 333 fCPU 247 1647 w 272 fCPU 247 136 w 272 fCPU 247 1647 w Block verify library 179 fCPU 12964 136 fCPU 12964 Self programming end library 34 fCPU Option value 03H 180 fCPU 261 134 fCPU 261 Option value 04H 190 fCPU 254 144 fCPU 254 Get information library Option value 05H 350 fCPU 213 304 fCPU 213 Set information library 80 fCPU 42839 80 fCPU 572592 72 fCPU 42839 72 fCPU 5725...

Page 610: ...cillation mode register RCM 2 When high speed system clock is used normal model of C compiler Interrupt Response Time μs Max RSTOP 0 RSTS 1 RSTOP 1 Library Name Entry RAM location is outside short direct addressing range Entry RAM location is in short direct addressing range Entry RAM location is outside short direct addressing range Entry RAM location is in short direct addressing range Block bla...

Page 611: ...67 136 fCPU 246 136 fCPU 1708 136 fCPU 569 Block erase library 136 fCPU 780 136 fCPU 459 136 fCPU 1921 136 fCPU 782 Word write library 272 fCPU 763 272 fCPU 443 272 fCPU 1871 272 fCPU 767 Block verify library 136 fCPU 580 136 fCPU 259 136 fCPU 1721 136 fCPU 582 Set information library 72 fCPU 456 72 fCPU 200 72 fCPU 1598 72 fCPU 459 19 fCPU 767 19 fCPU 447 19 fCPU 767 19 fCPU 447 EEPROM write libr...

Page 612: ...he program has been correctly written to boot cluster 0 restore the original boot area by using the set information function of the firmware of the 78K0 Kx2 A microcontrollers Note A boot cluster is a 4 KB area and boot clusters 0 and 1 are swapped by the boot swap function Boot cluster 0 0000H to 0FFFH Original boot program area Boot cluster 1 1000H to 1FFFH Area subject to boot swap function Cau...

Page 613: ... program Boot program Boot program New boot program New boot program New boot program New boot program Boot program 3 2 1 0 7 6 5 4 Boot program Boot program Boot program New boot program New boot program New boot program New boot program Erasing block 0 Erasing block 1 Erasing block 2 Erasing block 3 3 2 1 0 7 6 5 4 Boot program Boot program Boot program New boot program New boot program New boot...

Page 614: ...ed NEC Electronics is not liable for problems occurring when the on chip debug function is used Figure 26 1 Connection Example of QB MINI2 and 78K0 Kx2 A microcontrollers When OCD0A X1 and OCD0B X2 Are Used VDD Target device P31 FLMD0 X1 OCD0A X2 OCD0B Reset signal RESET_INNote 1 DATA CLK FLMD0 RESET VDD RESET_OUT GND Target connector 10 pin GND Note 2 VDD Reset circuit VDD VDD GND R F U R F U Not...

Page 615: ...resistance 100 Ω or less For details refer to QB MINI2 User s Manual U18371E 2 This is the processing of the pin when OCD1B P32 is set as the input port to prevent the pin from being left opened when not connected to QB MINI2 3 Make pull down resistor 470 Ω or more 10 kΩ recommended Connect the FLMD0 pin as follows when performing self programming by means of on chip debugging Figure 26 3 Connecti...

Page 616: ...ions When using a boot swap operation during self programming set the same value to boot cluster 1 beforehand For details on reserved area refer to QB MINI2 User s Manual U18371E Figure 26 4 Reserved Area Used by QB MINI2 Debug monitor area 2 bytes Software break area 2 bytes Security ID area 10 bytes Option byte area 1 byte Debug monitor area 257 bytes Pseudo RRM area 256 bytes Internal ROM space...

Page 617: ...bel When using a label be sure to write the and symbols For operand register identifiers r and rp either function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for specification Table 27 1 Operand Identifiers and Specification Methods Identifier Specification Method r rp sfr sfrp X R0 A R1 C R2 B R3 E R4 D R5 L R6 H R7 AX RP0 BC RP1 DE RP2 HL RP...

Page 618: ... word CY Carry flag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag Memory contents indicated by address or register contents in parentheses XH XL Higher 8 bits and lower 8 bits of 16 bit register Logical product AND Logical sum OR Exclusive logical sum exclusive OR Inverted data addr16 16 bit immediate data or label jdisp8 Signed 8 bit data displ...

Page 619: ... HL A A HL byte 2 8 9 A HL byte HL byte A 2 8 9 HL byte A A HL B 1 6 7 A HL B HL B A 1 6 7 HL B A A HL C 1 6 7 A HL C MOV HL C A 1 6 7 HL C A A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A addr16 3 8 10 A addr16 A DE 1 4 6 A DE A HL 1 4 6 A HL A HL byte 2 8 10 A HL byte A HL B 2 8 10 A HL B 8 bit data transfer XCH A HL C 2 8 10 A HL C Notes 1 When the internal high speed RAM area is ac...

Page 620: ...CY A addr16 A HL 1 4 5 A CY A HL A HL byte 2 8 9 A CY A HL byte A HL B 2 8 9 A CY A HL B ADD A HL C 2 8 9 A CY A HL C A byte 2 4 A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4 r CY r A CY A saddr 2 4 5 A CY A saddr CY A addr16 3 8 9 A CY A addr16 CY A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY 8 bit operation ADDC ...

Page 621: ...dr16 3 8 9 A CY A addr16 CY A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY SUBC A HL C 2 8 9 A CY A HL C CY A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byte A r Note 3 2 4 A A r r A 2 4 r r A A saddr 2 4 5 A A saddr A addr16 3 8 9 A A addr16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B 8 bit operation AND A HL C 2 8 9 A A HL C Note...

Page 622: ...6 3 8 9 A A addr16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B XOR A HL C 2 8 9 A A HL C A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2 4 5 A saddr A addr16 3 8 9 A addr16 A HL 1 4 5 A HL A HL byte 2 8 9 A HL byte A HL B 2 8 9 A HL B 8 bit operation CMP A HL C 2 8 9 A HL C Notes 1 When the internal high speed RAM area is accessed or f...

Page 623: ...HL 3 0 HL 7 4 A3 0 HL 3 0 HL 7 4 Rotate ROL4 HL 2 10 12 A3 0 HL 7 4 HL 3 0 A3 0 HL 7 4 HL 3 0 ADJBA 2 4 Decimal Adjust Accumulator after Addition BCD adjustment ADJBS 2 4 Decimal Adjust Accumulator after Subtract CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit CY A bit 2 4 CY A bit CY PSW bit 3 7 CY PSW bit CY HL bit 2 6 7 CY HL bit saddr bit CY 3 6 8 saddr bit CY sfr bit CY 3 8 sfr bit ...

Page 624: ...CY CY A bit CY PSW bit 3 7 CY CY PSW bit XOR1 CY HL bit 2 6 7 CY CY HL bit saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 SET1 HL bit 2 6 8 HL bit 1 saddr bit 2 4 6 saddr bit 0 sfr bit 3 8 sfr bit 0 A bit 2 4 A bit 0 PSW bit 2 6 PSW bit 0 CLR1 HL bit 2 6 8 HL bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 Bit manipulate NOT1 CY 1 2 CY CY Notes 1 When the int...

Page 625: ...SP 1 PUSH rp 1 4 SP 1 rpH SP 2 rpL SP SP 2 PSW 1 2 PSW SP SP SP 1 R R R POP rp 1 4 rpH SP 1 rpL SP SP SP 2 SP word 4 10 SP word SP AX 2 8 SP AX Stack manipulate MOVW AX SP 2 8 AX SP addr16 3 6 PC addr16 addr16 2 6 PC PC 2 jdisp8 Unconditional branch BR AX 2 8 PCH A PCL X BC addr16 2 6 PC PC 2 jdisp8 if CY 1 BNC addr16 2 6 PC PC 2 jdisp8 if CY 0 BZ addr16 2 6 PC PC 2 jdisp8 if Z 1 Conditional branc...

Page 626: ...C PC 4 jdisp8 if sfr bit 1 then reset sfr bit A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 then reset A bit PSW bit addr16 4 12 PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit BTCLR HL bit addr16 3 10 12 PC PC 3 jdisp8 if HL bit 1 then reset HL bit B addr16 2 6 B B 1 then PC PC 2 jdisp8 if B 0 C addr16 2 6 C C 1 then PC PC 2 jdisp8 if C 0 Conditional branch DBNZ saddr addr16 3 8 10 saddr saddr 1 then...

Page 627: ...None A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP ROR ROL RORC ROLC r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP INC DEC B C DBNZ sfr MOV MOV saddr MOV ADD ADDC SUB SUBC AND OR XOR CMP MO...

Page 628: ...VW MOVW addr16 MOVW SP MOVW MOVW Note Only when rp BC DE HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand First Operand A bit sfr bit saddr bit PSW bit HL bit CY addr16 None A bit MOV1 BT BF BTCLR SET1 CLR1 sfr bit MOV1 BT BF BTCLR SET1 CLR1 saddr bit MOV1 BT BF BTCLR SET1 CLR1 PSW bit MOV1 BT BF BTCLR SET1 CLR1 HL bit MOV1 BT BF BTCLR SET1 CLR1 CY MO...

Page 629: ...tructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand First Operand AX addr16 addr11 addr5 addr16 Basic instruction BR CALL BR CALLF CALLT BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ 5 Other instructions ADJBA ADJBS BRK RET RETI RETB SEL NOP EI DI HALT STOP ...

Page 630: ...y may be exceeded when this function is used and product reliability therefore cannot be guaranteed NEC Electronics is not liable for problems occurring when the on chip debug function is used 2 The pins mounted depend on the product as follows 1 Port functions 78K0 KB2 A 78K0 KC2 A Port 30 Pins 48 Pins Port 0 P00 to P02 Port 1 P10 to P13 Port 2 P20 to P25 P20 to P27 Port 3 P31 P32 P35 P31 to P35 ...

Page 631: ...LK Writing to flash memory FLMD0 Interrupt INTP0 INTP1 INTP4 to INTP7 INTP0 to INTP9 Key interrupt KR0 to KR5 TM00 TI000 TI010 TO00 TM50 TI50 TO50 TM51 TI51 TO51 TMH0 TOH0 Timer TMH1 TOH1 UART6 RxD6 TxD6 IICA SCLA0 SDAA0 Serial CSI10 SCK10 SI10 SO10 SCK10 SI10 SO10 SSI10 A D converter ANI0 to ANI5 ANI8 to ANI11 ANI0 to ANI6 ANI8 to ANI11 ANI15 Clock output PCL Real time counter output RTC1HZ RTCCL...

Page 632: ...DD 0 3 Note V Output voltage VO2 P20 to P27 P80 to P83 0 3 to AVDD 0 3 Note V Analog input voltage VAN1 ANI0 to ANI6 ANI8 to ANI11 ANI15 AMP0 AMP1 AMP2 AMP0 AMP1 AMP2 0 3 to AVDD 0 3 Note and 0 3 to VDD 0 3 Note V Analog output voltage VANO1 AMP0OUT AMP1OUT AMP2OUT 0 3 to AVDD 0 3 V AVREFP 0 3 to AVDD 0 3 Note V Anarog reference voltage input AVREFM 0 3 to AVDD 0 3 Note and AVREFM AVREFP Note V No...

Page 633: ... 200 mA P10 to P13 P31 to P35 P60 P61 P70 to P75 140 mA Per pin 1 mA Total of all pins P20 to P27 P80 to P83 5 mA Per pin 4 mA Total of all pins P121 to P124 10 mA Per pin 1 mA Output current low IOL Total of all pins AMP0OUT AMP1OUT AMP2OUT 3 mA Operating ambient temperature TA 40 to 85 C Storage temperature Tstg 65 to 150 C Cautions 1 Product quality may suffer if the absolute maximum rating is ...

Page 634: ...broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as VSS Do not ground the capacitor to a ground patter...

Page 635: ...ter Conditions MIN TYP MAX Unit Crystal resonator XT1 VSS XT2 C4 C3 Rd XT1 clock oscillation frequency fXT Note 2 32 32 768 35 kHz Notes 1 The 78K0 KB2 A is not provided with the XT1 oscillator 2 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time Cautions 1 When using the XT1 oscillator wire as follows in the area enclosed by the broken lines in th...

Page 636: ...P42 P120 Note 3 1 8 V VDD 2 7 V 9 0 mA 4 0 V VDD 5 5 V 45 0 mA 2 7 V VDD 4 0 V 35 0 mA Total of P10 to P13 P31 to P35 P60 P61 P70 to P75 Note 3 1 8 V VDD 2 7 V 20 0 mA 4 0 V VDD 5 5 V 65 0 mA 2 7 V VDD 4 0 V 50 0 mA IOL1 Total of all the pins above Note 3 1 8 V VDD 2 7 V 29 0 mA Per pin for P20 to P27 P80 to P83 AVDD VDD 0 4 mA Output current low Note 2 IOL2 Per pin for P121 to P124 0 4 mA Notes 1...

Page 637: ...D AVDD V Input voltage high VIH4 P60 P61 0 7VDD 6 0 V VIL1 P40 P41 P60 P61 P121 to P124 EXCLK 0 0 3VDD V VIL2 P00 to P02 P10 to P13 P31 to P35 P42 P70 to P75 P120 RESET 0 0 2VDD V Input voltage low VIL3 P20 to P27 P80 to P83 AVDD VDD 0 0 3AVDD V 4 0 V VDD 5 5 V IOH1 3 0 mA VDD 0 7 V 2 7 V VDD 4 0 V IOH1 2 5 mA VDD 0 5 V VOH1 P00 to P02 P10 to P13 P31 to P35 P40 to P42 P70 to P75 P120 1 8 V VDD 2 7...

Page 638: ...5 0 mA 0 6 V 2 7 V VDD 4 0 V IOL1 3 0 mA 0 4 V Output voltage low VOL3 P60 P61 1 8 V VDD 2 7 V IOL1 2 0 mA 0 4 V ILIH1 P00 to P02 P10 to P13 P31 to P35 P40 to P42 P60 P61 P70 to P75 P120 FLMD0 RESET VI VDD 1 μA ILIH2 P20 to P27 P80 to P83 VI AVDD AVDD VDD 1 μA I O port mode 1 μA Input leakage current high ILIH3 P121 to 124 X1 X2 XT1 XT2 VI VDD OSC mode 20 μA ILIL1 P00 to P02 P10 to P13 P31 to P35 ...

Page 639: ...DD 5 0 V Note 5 Resonator connection 11 30 μA IDD1 Operating mode fSUB 32 768 kHz VDD 3 0 V Note 5 Resonator connection 6 28 μA Square wave input 0 8 2 6 mA fXH 20 MHz VDD 5 0 V Note 2 Resonator connection 2 0 4 4 mA Square wave input 0 8 2 6 mA fXH 20 MHz VDD 3 0 V Note 2 Resonator connection 1 7 4 1 mA Square wave input 0 4 1 3 mA fXH 10 MHz VDD 5 0 V Notes 2 3 Resonator connection 1 0 2 4 mA Sq...

Page 640: ...ter operational amplifier watchdog timer and LVI circuit 3 When AMPH bit 0 of clock operation mode select register OSCCTL 0 4 Not including the operating current of the X1 oscillator XT1 oscillator and 240 kHz internal oscillator and the current flowing into the A D converter operational amplifier watchdog timer and LVI circuit 5 Not including the operating current of the X1 oscillator 8 MHz inter...

Page 641: ... and IWDT when the watchdog timer operates 2 Current flowing only to the LVI circuit The current value of the 78K0 Kx2 A microcontrollers is the sum of IDD1 IDD2 or IDD3 and ILVI when the LVI circuit operates 3 Current flowing only to the A D converter AVDD The current value of the 78K0 Kx2 A microcontrollers is the sum of IDD1 or IDD2 and IADC when the A D converter operates in an operation mode ...

Page 642: ...V VDD 4 0 V 2 fsam 0 2 Note 6 μs TI000 TI010 input high level width low level width tTIH0 tTIL0 1 8 V VDD 2 7 V 2 fsam 0 5 Note 6 μs 4 0 V VDD 5 5 V 10 MHz 2 7 V VDD 4 0 V 10 MHz TI50 TI51 input frequency fTI5 1 8 V VDD 2 7 V 5 MHz 4 0 V VDD 5 5 V 50 ns 2 7 V VDD 4 0 V 50 ns TI50 TI51 input high level width low level width tTIH5 tTIL5 1 8 V VDD 2 7 V 100 ns Interrupt input high level width low lev...

Page 643: ...on the product Refer to Caution 2 at the beginning of this chapter TCY vs VDD Main System Clock Operation 5 0 1 0 2 0 0 4 0 2 0 1 0 10 1 0 2 0 3 0 4 0 5 0 6 0 5 5 2 7 100 0 01 1 8 32 Supply voltage VDD V Cycle time T CY s Guaranteed operation range The gray portion is applicable only if AMPH 1 is set μ ...

Page 644: ...uct Refer to Caution 2 at the beginning of this chapter AC Timing Test Points VIH VIL Test points VIH VIL External Main System Clock Timing EXCLK 0 7VDD MIN 0 3VDD MAX 1 fEXCLK tEXCLKL tEXCLKH TI Timing TI000 TI010 tTIL0 tTIH0 TI50 TI51 1 fTI5 tTIL5 tTIH5 Interrupt Request Input Timing INTP0 to INTP9 tINTL tINTH ...

Page 645: ...AL SPECIFICATIONS User s Manual U19780EJ2V0UD 643 Caution The pins mounted depend on the product Refer to Caution 2 at the beginning of this chapter Key Interrupt Input Timing KR0 to KR5 tKR RESET Input Timing RESET tRSL ...

Page 646: ... tLOW 4 7 1 3 μs Hold time when SCLA0 H tHIGH 4 0 0 6 μs Data setup time reception tSU DAT 250 100 ns Data hold time transmission Notes 2 3 tHD DAT 0 3 45 0 0 9 μs Setup time of stop condition tSU STO 4 0 0 6 μs Bus free time between stop condition and start condition tBUF 4 7 1 3 μs Rise time of SDAA0 and SCLA0 signals tR 1000 2 0 0 1Cb 300 ns Fall time of SDAA0 and SCLA0 signals tF 300 2 0 0 1 C...

Page 647: ...K1 1 8 V VDD 2 7 V 170 ns SI10 hold time from SCK10 tKSI1 30 ns Delay time from SCK10 to SO10 output tKSO1 C 50 pF Note 3 40 ns Notes 1 The master mode can be used only when bit 2 ISC2 of the input switch control register ISC is set to 1 2 This value is when high speed system clock fXH is used 3 C is the load capacitance of the SCK10 and SO10 output lines d CSI10 slave mode SCK10 external clock in...

Page 648: ...Refer to Caution 2 at the beginning of this chapter Serial Transfer Timing IICA tLOW tR tHIGH tF tHD STA tBUF Stop condition Start condition Restart condition Stop condition tSU DAT tSU STA tSU STO tHD STA tHD DAT SCLA0 SDAA0 CSI10 SI10 SO10 tKCYm tKLm tKHm tSIKm tKSIm Input data tKSOm Output data SCK10 Remark m 1 2 ...

Page 649: ...EF 46 220 μA b TA 40 to 85 C 1 8 V AVREFP AVDD 1 8 V AVDD VDD 5 5 V VSS AVSS AVREFM 0 V Parameter Symbol Conditions MIN TYP MAX Unit Resolution RES 12 12 12 bit 2 3 V AVREFP 5 5 V 2 0 12 LSB Overall error Note 1 AINL 1 8 V AVREFP 2 3 V 3 0 12 LSB Normal mode 1 2 Note 2 5 μs Conversion time tCONV Low voltage mode Note 2 21 μs Zero scale error Note 1 EZS 2 0 10 0 LSB Full scale error Note 1 EFS 2 0 ...

Page 650: ...quantization error 1 2 LSB 2 The voltage range that can be used on each mode is as follows Normal mode 1 2 7 V AVDD 5 5 V Normal mode 2 2 3 V AVDD 5 5 V Low voltage mode 1 8 V AVDD 5 5 V When using the A D converter in Normal mode 2 or low voltage mode be sure to enable the A D converter voltage booster by setting VRGV to 1 2 Operational amplifier TA 40 to 85 C 2 0 V AVDD VDD 5 5 V VSS AVSS 0 V Pa...

Page 651: ...POC Circuit Timing Supply voltage VDD Time Detection voltage MIN Detection voltage TYP Detection voltage MAX tPTH tPW Supply Voltage Rise Time TA 40 to 85 C VSS 0 V Parameter Symbol Conditions MIN TYP MAX Unit Maximum time to rise to 1 8 V VDD MIN VDD 0 V 1 8 V tPUP1 POCMODE option byte 0 when RESET input is not used 3 6 ms Maximum time to rise to 1 8 V VDD MIN releasing RESET input VDD 1 8 V tPUP...

Page 652: ...ration A reset state is retained until VPOC 1 59 V TYP is reached after the power is turned on and the reset is released when VPOC is exceeded After that POC detection is performed at VPOC similarly as when the power was turned on The power supply voltage must be raised at a time of tPUP1 or tPUP2 when POCMODE is 0 POCMODE 1 2 7 V 1 59 V mode operation A reset state is retained until VDDPOC 2 7 V ...

Page 653: ...LVI10 2 60 2 70 2 80 V VLVI11 2 45 2 55 2 65 V VLVI12 2 29 2 39 2 49 V VLVI13 2 14 2 24 2 34 V VLVI14 1 98 2 08 2 18 V Supply voltage level VLVI15 1 83 1 93 2 03 V Detection voltage External input pin Note 1 EXLVI EXLVI VDD 1 8 V VDD 5 5 V 1 11 1 21 1 31 V Minimum pulse width tLW 200 μs Operation stabilization wait time Note 2 tLWAIT 10 μs Notes 1 The EXLVI P120 INTP0 pin is used 2 Time required f...

Page 654: ...aracteristics TA 40 to 85 C Parameter Symbol Conditions MIN TYP MAX Unit Data retention supply voltage VDDDR 1 44 Note 5 5 V Note The value depends on the POC detection voltage When the voltage drops the data is retained until a POC reset is effected but data is not retained when a POC reset is effected VDD STOP instruction execution Standby release signal interrupt request STOP mode Data retentio...

Page 655: ...ites per chip Cerwr 1 erase 1 write after erase 1 rewrite Note 3 Conditions other than the above Note 6 Retention 10 years 100 Times Notes 1 Characteristic of the flash memory 2 The prewrite time before erasure and the erase verify time writeback time are not included 3 When a product is first written after shipment erase write and write only are both taken as one rewrite 4 The sample library spec...

Page 656: ...Each lead centerline is located within 0 13 mm of its true position T P at maximum material condition ITEM DIMENSIONS A B C E F G H I J L M N D 0 30 0 65 T P 0 10 0 05 1 30 0 10 1 20 8 10 0 20 6 10 0 10 1 00 0 20 0 50 0 13 0 10 0 22 0 10 0 05 K 0 15 0 05 0 01 P 3 5 3 UNIT mm P30MC 65 CAB V W W A I F G E C N D M B K H J P U T L 9 70 0 10 T U V 0 25 T P 0 60 0 15 0 25 MAX W 0 15 MAX 15 ...

Page 657: ...E A3 S 0 125 0 075 0 025 UNIT mm ITEM DIMENSIONS D E HD HE A A1 A2 A3 7 00 0 20 7 00 0 20 9 00 0 20 9 00 0 20 1 60 MAX 0 10 0 05 1 40 0 05 0 25 c θ e x y ZD ZE 0 50 0 08 0 08 0 75 0 75 L Lp L1 0 50 0 60 0 15 1 00 0 20 P48GA 50 GAM 3 5 3 NOTE Each lead centerline is located within 0 08 mm of its true position at maximum material condition detail of lead end 0 20 b 12 24 1 48 13 25 37 36 0 07 0 03 ...

Page 658: ...xt instruction processing but waits If this happens the number of execution clocks of an instruction increases by the number of wait clocks for the number of wait clocks see Table 30 1 This must be noted when real time processing is performed 30 2 Peripheral Hardware That Generates Wait Table 30 1 lists the registers that issue a wait request when accessed by the CPU and the number of CPU wait clo...

Page 659: ...Published by NEC Electronics Corporation http www necel com Contact http www necel com support ...

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