Renesas 78K0 Series, User Manual, Page: 166 / 659

CHAPTER 5 CLOCK GENERATOR
User’s Manual U19780EJ2V0UD
164
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (5/5)
(11)
•
STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
•
STOP mode (I) set while CPU is operating with high-speed system clock (C)
(Setting sequence)
Status Transition Setting
(B)
→
(H)
(C)
→
(I)
Stopping peripheral functions that
cannot operate in STOP mode
Executing STOP instruction
Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figures 5-15 and 5-16.
2. EXCLK, OSCSEL, AMPH: Bits 7, 6 and 0 of the clock operation mode select register (OSCCTL)
MSTOP: Bit 7 of the main OSC control register (MOC)
XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM)
CSS: Bit 4 of the processor clock control register (PCC)
5.6.7 Condition before changing CPU clock and processing after changing CPU clock
Condition before changing the CPU clock and processing after changing the CPU clock are shown below.
Table 5-6. Changing CPU Clock (1/2)
(1) 78K0/KB2-A
CPU Clock
Before Change After Change
Condition Before Change Processing After Change
X1 clock Stabilization of X1 oscillation
•
MSTOP = 0, OSCSEL = 1, EXCLK = 0
•
After elapse of oscillation stabilization time
•
Internal high-speed oscillator can be
stopped (RSTOP = 1).
•
Clock supply to CPU is stopped for 4.06 to
16.12
μ
s after AMPH has been set to 1.
Internal high-
speed
oscillation
clock
External main
system clock
Enabling input of external clock from EXCLK
pin
•
MSTOP = 0, OSCSEL = 1, EXCLK = 1
•
Internal high-speed oscillator can be
stopped (RSTOP = 1).
•
Clock supply to CPU is stopped for the
duration of 160 external clocks from the
EXCLK pin after AMPH has been set to 1.
X1 clock X1 oscillation can be stopped (MSTOP = 1).
External main
system clock
Internal high-
speed
oscillation
clock
Oscillation of internal high-speed oscillator
•
RSTOP = 0
External main system clock input can be
disabled (MSTOP = 1).