1260-00C User Manual
Local Command Set 4-52
43
Connection to EXTCLK input pin
44 to 49
Hardware-dependent GPIOs 4 to 9
50
TIC counter pulse output (TCNTR)
51
TIC counter finished output (GCNTR)
60
TIC TICK1 tick timer output
61
TIC TICK2 tick timer output
and the value of
<mode>
specifies the signal
conditioning mode (where 0 = no conditioning). The
conditioning effects for bits 0 to 3 are as follows:
Bit Conditioning Effect
0
Synchronize with next CLK edge
1
Invert signal polarity
2
Pulse stretch to one CLK minimum
3
Use EXTCLK (not CLK10) for conditioning
Response:
Program response: 0
Console response:
Mapping complete (line = <line text
source> mapped to line = <line text
destination>, mode = <mode>)
.<CRLF>
where the meaning of
<line text source>
and
<line text destination>
correspond to the
value of
<srcTrig>
and
<destTrig>
as
follows:
Value of
<srcTrig>
Value of
<line text
source>
or <destTrig>
or
<line text destination>
0 to 7
TTL <line>
8 to 9
ECL (<line> - 8)
40 to 49
GPIO (<line> - 40)
50
TCNTR
51
GCNTR
60
TICK1
61
TICK2
Example:
Map TTL line 4 to go out of the front panel with no
signal conditioning.
MapTrigTrig 4, 41, 0
SetTrigHndlr
Purpose:
Replace the current TTL/ECL trigger, counter, or
tick timer interrupt handler with a specified trigger
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