QUANTA W Mainboard Series S210-MBT2W, Technical Manual

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A
BOUT THE
S
ERVER
MEMHOT#
1-77
SNB-EP / IVB-EP Processors and the ASPEED AST2300 BMC
Serial GPIO expander is there as a backup.
[1.3.206] The Sandy Bridge -EP and Ivy Bridge –EP Proces-
sors also support a feature which allows an external source to
disable the SNB-EP / IVB-EP Processor socket via PRO-
CHOT#. In order to place the Sandy Bridge –EP / Ivy Bridge –
EP Processor socket in “tri-state” mode an external agent (in
this case the ASPEED AST2300) must drive the PROCHOT#
(INPUT mode on SNB-EP / IVB-EP Processor) signal low while
the CPU_RST# signal transitions from asserted (LOW) to de-
asserted (HIGH.) This will place the associated SNB-EP / IVB-
EP socket in “tri-state” mode thereby disabling it. Only the SNB-
EP / IVB-EP Socket 1 (non-legacy) will support this function on
the Romley platform.
[1.3.207] An external source can also toggle the PROCHOT#
(INPUT mode on SNB-EP / IVB-EP Processor) to force the Pro-
cessor into throttling mode. This usually happens when the sys-
tem reaches a certain thermal threshold. In the Romley platform
implementation, VRHOT# is an output of the SNB-EP / IVB-EP
Processor VR12.0 controller, which is capable of throttling the
Processor via PROCHOT#.
[1.3.209] MEMHOT#
[1.3.210] MEMHOT# is a bi-directional signal. The SNB-EP /
IVB-EP Uncore (Memory Controller) drives the MEMHOT#
(OUTPUT mode on SNB-EP / IVB-EP Uncore logic) active
LOW when it goes into throttling mode. The duty cycle of MEM-
HOT# toggling over a period of time indicates the approximate
temperature between a configurable lower temperature register
and the hottest DIMM temperature initiated by the SNB-EP /
IVB-EP Memory Controller. Firmware monitors the MEMHOT#
signals on the SNB-EP / IVB-EP Controller to determine Mem-
ory throttling events. The ASPEED AST2300 BMC can then
query the Memory Controller Uncore registers to identify which
memory channels are throttling and at what rate.
[1.3.211] An external source can also toggle the MEMHOT#
(INPUT mode on SNB-EP / IVB-EP Uncore Logic) to force the
Memory Controller to go into throttling mode. This usually hap-
pens when the system reaches a certain power threshold. In
the Romley platform implementation, VRHOT# is an output
from the Memory Subsystem VR12.0 controller, which is capa-
ble of throttling the SNB-EP / IVB-EP Memory Controller via
MEMHOT#. Firmware monitors the Memory Subsystem
VR12.0 VRHOT# and creates a SEL event if VRHOT# is
asserted
Note:
[1.3.208] Some simple masking circuitry is required to pre-
vent the Processor VR12.0 VRHOT# signal from asserting
the PROCHOT# to the SNB-EP / IVB-EP Processor at the
time of CPU_RST#. This keeps the VRHOT# from uninten-
tionally causing the SNB-EP / IVB-EP Processor to be dis-
abled. Firmware monitors VRHOT# and creates a SEL event
if VRHOT# is asserted.