A
CRONYMS
XVIII
[0.3.10] Acronyms
[0.3.11]
TERM
[0.3.12]
DEFINITION
[0.3.13]
A/D
[0.3.14]
Analog to Digital
[0.3.15]
ACPI
[0.3.16]
Advanced Configuration and Power Interface
[0.3.17]
ASF
[0.3.18]
Alerting Standard Forum
[0.3.19]
Asserte
d
[0.3.20]
Active-high (positive true) signals are
asserted when in the high electrical state (near power
potential). Active-low (negative true) signals are
asserted when in the low electrical state (near ground
potential).
[0.3.21]
BIOS
[0.3.22]
Basic Input/Output System
[0.3.23]
BIST
[0.3.24]
Built-In Self Test
[0.3.25]
BMC
[0.3.26]
At the heart of the IPMI architecture is a
microcontroller called the Baseboard management
controller (BMC)
[0.3.27]
Bridge
[0.3.28]
Circuitry connecting one computer bus to
another, allowing an agent on one to access the other
[0.3.29]
BSP
[0.3.30]
Bootstrap processor
[0.3.31]
Byte
[0.3.32]
8-bit quantity
[0.3.33]
CLI
[0.3.34]
Command Line Interface
[0.3.35]
CMOS
[0.3.36]
In terms of this specification, this describes
the PC-AT compatible region of battery-backed 128
bytes of memory, which normally resides on the
baseboard
[0.3.37]
CPU
[0.3.38]
Central Processing Unit
[0.3.39]
Deasser
ted
[0.3.40]
A signal is deasserted when in the inactive
state. Active-low signal names have “_L” appended
to the end of the signal mnemonic. Active-high signal
names have no “_L” suffix. To reduce confusion when
referring to active-high and active-low signals, the
terms one/zero, high/low, and true/false are not used
when describing signal states.
[0.3.41]
DTC
[0.3.42]
Data Transfer Controller
[0.3.43]
EEPRO
M
[0.3.44]
Electrically Erasable Programmable Read-
Only Memory
[0.3.45]
EMP
[0.3.46]
Emergency Management Port
[0.3.47]
FRU
[0.3.48]
Field Replaceable Unit
[0.3.49]
GB
[0.3.50]
1024 MB.
[0.3.51]
GPIO
[0.3.52]
General Purpose Input/Out
[0.3.53]
HSC
[0.3.54]
Hot-Swap Controller
[0.3.55]
Hz
[0.3.56]
Hertz (1 cycle/second)
[0.3.57]
I
2
C
[0.3.58]
Inter-Integrated Circuit bus
[0.3.59]
IANA
[0.3.60]
Internet Assigned Numbers Authority
[0.3.61]
IBF
[0.3.62]
Input buffer
[0.3.63]
ICH
[0.3.64]
I/O Controller Hub
[0.3.65]
ICMB
[0.3.66]
Intelligent Chassis Management Bus
Summary of Contents for W Mainboard Series S210-MBT2W
Page 25: ... 1 0 1 About the Server Chapter 1 ...
Page 31: ... 1 3 31 Functional Architecture ...
Page 121: ... 2 0 1 BIOS Chapter 2 ...
Page 187: ... 3 0 1 BMC Chapter 3 ...
Page 265: ... 4 0 1 Jumpers and Connectors Chapter 4 ...
Page 270: ... 5 0 1 Troubleshooting Chapter 5 ...
Page 275: ... 6 0 1 Installation and Assembly Safety Instructions Chapter 6 ...
Page 280: ... 7 0 1 Safety Information Chapter 7 ...
Page 289: ... 8 0 1 Regulatory and Compliance Information Chapter 8 ...