A
BOUT
THE
S
ERVER
GPIO L
IST
1-72
67
AL15
GPIO66
I
P1V1_SSB
NA
"In Core Power Well.
Unmuxed. Defaults to
GPO. "
GPIO66
(GPO)
GPO
FM_RISE
R_ID2
high
connect
to
Slot5and
Slot6
and pull
up P3V3
via
1Kohm
P3V3
PCIE
slot6
riser
68
AK15
GPIO67
I
P1V1_SSB
NA
"In Core Power Well.
Unmuxed. Defaults to
GPO. "
GPIO67
(GPO)
GPO
FW_1394
_DISABLE
_N
Board
1394 dis-
able pin
P3V3
1394
disable
pin
69
AG34
TACH4_GPIO68
I
P1V1_SSB
PU
"In Core Power Well.
Muxed with TACH4.
Defaults to GPI. If not
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
TACH4
(GPI)
GPI
BOARD_R
EVISION1
high
PU to
P3V3 via
10K (NI)
and PD
via 10K
P3V3
board
revi-
sion ID
70
Y32
TACH5_GPIO69
I
P1V1_SSB
PU
"In Core Power Well.
Muxed with TACH5.
Defaults to GPI. If not
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
TACH5
(GPI)
GPI
"PCIE_SL
OT4_PRE
SENT_N"
high
Connect
to PCIE
slot4 and
PU to
P3V3 via
10K
P3V3
PCIE
slot4
pres-
ent pin
71
AF34
TACH6_GPIO70
I
P1V1_SSB
PU
"In Core Power Well.
Muxed with TACH6.
Defaults to GPI. If not
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
TACH6
(GPI)
GPI
PCIE_SL
OT5_PRE
SENT_N
high
Connect
to PCIE
slot5 and
PU to
P3V3 via
10K
P3V3
PCIE
slot5
pres-
ent pin
[1.3.195] GPIO List (Continued)
I
TEM
P
IN
#
P
IN
N
AME
IO
TYPE
P
OWER
WELL
PU/PD
V
ENDOR
R
ECOMMENDATIONS
(
REFERENCE
DESIGN
)
A
LTERNATE
FUNCTION
(D
EFAULT
)
U
SED
FUNCTION
NET
NAME
STATE
AFTER
RESET
N
ET
CONNECT
TO
Summary of Contents for W Mainboard Series S210-MBT2W
Page 25: ... 1 0 1 About the Server Chapter 1 ...
Page 31: ... 1 3 31 Functional Architecture ...
Page 121: ... 2 0 1 BIOS Chapter 2 ...
Page 187: ... 3 0 1 BMC Chapter 3 ...
Page 265: ... 4 0 1 Jumpers and Connectors Chapter 4 ...
Page 270: ... 5 0 1 Troubleshooting Chapter 5 ...
Page 275: ... 6 0 1 Installation and Assembly Safety Instructions Chapter 6 ...
Page 280: ... 7 0 1 Safety Information Chapter 7 ...
Page 289: ... 8 0 1 Regulatory and Compliance Information Chapter 8 ...