QUANTA W Mainboard Series S210-MBT2W, Technical Manual

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A
BOUT THE
S
ERVER
PCI-E
XPRESS
1-25
[1.3.3] PCI-Express
[1.3.4] Processor PCIe
[1.3.5] PCIe Gen1, Gen2 and Gen 3 are dual-simplex point-to
point serial differential low-voltage interconnects. The signaling
bit rate is 2.5 Gbit/s one direction per lane for Gen1 (8b/10b
encoding), 5.0 Gbit/s one direction per lane for Gen2 (8b/10b
encoding) and 8.0 Gbit/s one direction per lane for Gen3 (128b/
130b encoding). Each port consists of a transmitter and
receiver pair. A link between the ports of two devices is a collec-
tion of lanes (x1, x2, x4, x8, x16, etc.). All lanes within a port
must transmit data using the same frequency. 8.0 Gbit/s trans-
lates to 1.0 GB/s (one way), which corresponds to 2GB/s, 4GB/
s, 8GB/s and 16GB/s for x2, x4, x8, and x16 lanes respectively.
Since a given lane is simultaneously transmitting and receiving
data though separate Tx and Rx pairs, the effective, theoretical
data transfer rate is doubled (ie. 4GB/s, 8GB/s, 16GB/s and
32GB/s).
[1.3.6] Processor PCIe Port Connec-
tivity
[1.3.7] The following table includes information on processor
PCIe port connectivity:
[1.3.9] PCIe Power Management
[1.3.10] L0 and L3 power management states are supported on
all PCIe slots and embedded end points.
[1.3.11] GPGPU Support
[1.3.12] S210-MBT2W Server Platforms must support up to 2 x
full length, full height, double-wide, 300W GPGPUs (General
[1.3.8] CPU PCIe Connectivity
CPU# D
EVICE
P
HYSICAL
C
ONN
IOU# P
ORT
E
LECTRIC
AL
W
IDTH
CPU0 Slot 2 x16 1 3A-3D x16
CPU1 Slot 3 x16 1 3A-3D x16
CPU0 LAN N/A 2 1A x4
CPU0 PGB N/A 2 1B x4
CPU0 PGB N/A DMI2 0 x4 Gen2
CPU1 Slot 4 x8 2 1A-1B x8
CPU0 Slot 5 x16 0 2A-2D x16
CPU1 Slot 6 x16 0 2A-2B x16