EN 187
3139 785 31532
9.
Circuit- and IC description
S D A
I / O
I2C Port Serial Data Input/Output .
A L S B
I / O
TTL Address Input. This signal sets up the LSB of the I2C address.
When this pin is tied low the I2C filter is activated which reduces noise on the
I2C interface.
V
DD_IO
P
Power supply for digital i/ps and o/ps
V
DD
P
Digital power supply
V
AA
P
Analog power supply
V
REF
I / O
Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235V).
E X T _ L F
I
External Loop filter for the internal PLL.
RTC_SCR_TR
I
Multifunctional Input: Real Time Control (RTC) input, Timing Reset input,
Subcarrier Reset input.
I
2
C
I
This Input Pin must be tied High (V
DD_IO
) for the ADV7310/ADV7311 to interface
over the I
2
C port.
G N D _ I O
PIN CONFIGURATION
1 2
1 3
14
1 5
17 1 8
3
4
5
6
7
1
2
10
11
8
9
56 5 5 5 4
57
5 8
5 9
6 0
47
53
4 2
4 3
4 4
4 5
4 0
4 1
3 8
3 9
1 9 2 0
DAC A
C
L
K
IN
_B
DA C B
AGND
VAA
R
T
C
_S
C
R
_
T
R
S
D
A
I2
C
A
LS
B
S
C
L
K
C
4
C
3
S
4
VDD_IO
Y 0
Y 1
Y 2
Y3
Y 4
Y5
Y 6
DAC D
C
7
C
5
P
_H
S
Y
N
C
C
L
K
IN
_
A
R
SE T
2
S
_H
S
Y
N
C
6 1
6 2
63
6 4
S_BLANK
DAC F
DAC C
P
_B
LA
N
K
C
9
C
8
G
N
D
_
IO
E XT_LF
16
21 2 2 2 3 2 4 2 5 2 6 2 7 2 8 29
30 3 1 32
37
35
3 3
3 4
COMP1
RES ET
DAC E
COMP2
V RE F
48
S
_V
S
Y
N
C
C
6
P
_
V
S
Y
N
C
49
5 0
51
52
S
0
S
1
46
Y7
VDD
Y9
C0
C1
C2
36
S
2
V
D
D
S
9
S
8
S
6
S
7
D
G
N
D
S
5
DG ND
Y 8
R
S ET
1
S
3
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
ADV7320
KSTZ
Figure 9-19
