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9.
Circuit- and IC Description
IC7007 - UDA 1361S - Analogue to Digital Converter
BLOCK DIAGRAM, PIN DESCRIPTION AND CONFIGURATION
handbook, full pagewidth
UDA1361TS
MGT451
1
VINL
ADC
Σ Δ
DIGITAL
INTERFACE
DC-CANCELLATION
FILTER
DECIMATION
FILTER
CLOCK
CONTROL
3
16
VINR
ADC
Σ Δ
13
DATAO
11
BCK
12
WS
6
SFOR
7
PWON
14
MSSEL
15
10
VSSD
9
VDDD
VSSA
5
VRP
4
VRN
2
Vref
8
SYSCLK
VDDA
Fig.1 Block diagram.
PINNING
SYMBOL
PIN
DESCRIPTION
V
INL
1
left channel input
V
ref
2
reference voltage
V
INR
3
right channel input
V
RN
4
negative reference voltage
V
RP
5
positive reference voltage
SFOR
6
data format selection input
PWON
7
power control input
SYSCLK
8
system clock 256, 384, 512 or 768f
s
V
DDD
9
digital supply voltage
V
SSD
10
digital ground
BCK
11
bit clock input/output
WS
12
word select input/output
DATAO
13
data output
MSSEL
14
master/slave select
V
SSA
15
analog ground
V
DDA
16
analog supply voltage
handbook, halfpage
UDA1361TS
MGT452
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VINL
Vref
VINR
VRN
VRP
SFOR
PWON
SYSCLK
VDDD
VSSD
BCK
WS
DATAO
MSSEL
VSSA
VDDA
Fig.2 Pin configuration.
Figure 9-8